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Tue, 30 Jun 2020 08:11:21 +0000 (UTC) Subject: Re: [PULL 00/63] riscv-to-apply queue To: LIU Zhiwei , Alistair Francis , Peter Maydell References: <20200626214410.3613258-1-alistair.francis@wdc.com> <544fb149-c920-b396-7297-f9688a744445@c-sky.com> From: Thomas Huth Message-ID: <29f57b2e-7d67-5da2-0ad0-0750e400a91c@redhat.com> Date: Tue, 30 Jun 2020 10:11:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <544fb149-c920-b396-7297-f9688a744445@c-sky.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=thuth@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=207.211.31.81; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/30 02:00:02 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 30/06/2020 08.56, LIU Zhiwei wrote: > > > On 2020/6/29 6:51, Alistair Francis wrote: >> On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell >> wrote: >>> On Fri, 26 Jun 2020 at 22:53, Alistair Francis >>> wrote: >>>> The following changes since commit >>>> 553cf5d7c47bee05a3dec9461c1f8430316d516b: >>>> >>>>    Merge remote-tracking branch >>>> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging >>>> (2020-06-26 18:22:36 +0100) >>>> >>>> are available in the Git repository at: >>>> >>>>    git@github.com:alistair23/qemu.git >>>> tags/pull-riscv-to-apply-20200626-1 >>>> >>>> for you to fetch changes up to >>>> b39d59434ea10649fdb9e0a339c30c76e38c5e17: >>>> >>>>    target/riscv: configure and turn on vector extension from command >>>> line (2020-06-26 14:22:15 -0700) >>>> >>>> ---------------------------------------------------------------- >>>> This PR contains two patches to improve PLIC support in QEMU. >>>> >>>> The rest of the PR is adding support for the v0.7.1 RISC-V vector >>>> extensions. This is experimental support as the vector extensions are >>>> still in a draft state. >>>> >>> Hi; I'm afraid this fails to build on PPC64 and s390x (ie >>> our big-endian hosts): > Hi Peter, > > Do you mean you built the patch set on PPC64 or s390x and got errors in > the list? Or just a worry? > > I have built the patch set on Ubuntu 18.04 X86-64. I don't know which > compile option > will fails the compilation. If you compiled on Ubuntu x86-64, could you > show me the > compile option? The related code in your patch "target/riscv: add vector stride load and store instructions" is in a "#ifdef HOST_WORDS_BIGENDIAN" section, so of course this bug does not trigger on a x86 host. You could temporarily turn the "#ifdef HOST_WORDS_BIGENDIAN" into a "#if 1" to see whether you can then also reproduce the error on x86. > As a note: I try to find a PPC64 for test, but I'm afraid it will be too > later. > Is there an available  PPC64  machine in the community? Maybe the easiest way to test your code on a big endian machine, too, is to get a github account, clone the QEMU repository there, and enable Travis for that repo. Then your code gets built on some non-x86 architectures (including a big-endian s390x) as soon as you push it to the repo (see .travis.yml for details). >>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function >>> ‘vext_clear’: >>> /home/ubuntu/qemu/target/riscv/vector_helper.c: In function >>> ‘vext_clear’: >>> /home/ubuntu/qemu/target/riscv/vector_helper.c:154:21: error: invalid >>> operands to binary & (have ‘void *’ and ‘long long unsigned int’) >>>           memset(tail & ~(7ULL), 0, part1); You obviously must not use "&" with a pointer. I guess you have to cast to "uintptr_t" and back, or think of some other smart way to fix this. Thomas