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Tue, 27 Jun 2023 14:19:46 -0700 (PDT) Message-ID: <29ffa6db-a4ed-0e67-2995-951248e8302e@linaro.org> Date: Tue, 27 Jun 2023 23:19:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v5 01/19] target/riscv: skip features setup for KVM CPUs Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com References: <20230627163203.49422-1-dbarboza@ventanamicro.com> <20230627163203.49422-2-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230627163203.49422-2-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.103, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, On 27/6/23 18:31, Daniel Henrique Barboza wrote: > As it is today it's not possible to use '-cpu host' if the RISC-V host > has RVH enabled. This is the resulting error: > > $ sudo ./qemu/build/qemu-system-riscv64 \ > -machine virt,accel=kvm -m 2G -smp 1 \ > -nographic -snapshot -kernel ./guest_imgs/Image \ > -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ > -append "earlycon=sbi root=/dev/ram rw" \ > -cpu host > qemu-system-riscv64: H extension requires priv spec 1.12.0 > > This happens because we're checking for priv spec for all CPUs, and > since we're not setting env->priv_ver for the 'host' CPU, it's being > default to zero (i.e. PRIV_SPEC_1_10_0). > > In reality env->priv_ver does not make sense when running with the KVM > 'host' CPU. It's used to gate certain CSRs/extensions during translation > to make them unavailable if the hart declares an older spec version. It > doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec > checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs > are available [1]. > > 'priv_ver' is just one example. We're doing a lot of feature validation > and setup during riscv_cpu_realize() that it doesn't apply KVM CPUs. > Validating the feature set for those CPUs is a KVM problem that should > be handled in KVM specific code. > > The new riscv_cpu_realize_features() helper contains all validation > logic that are not applicable to KVM CPUs. riscv_cpu_realize() verifies > if we're dealing with a KVM CPU and, if not, execute the new helper to > proceed with the usual realize() logic for all other CPUs. > > [1] lib/sbi/sbi_hart.c, hart_detect_features() > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > Reviewed-by: Andrew Jones > --- > target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- > 1 file changed, 33 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fb8458bf74..e515dde208 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -331,6 +331,15 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) > } > #endif > > +static bool riscv_running_kvm(void) > +{ > +#ifndef CONFIG_USER_ONLY > + return kvm_enabled(); > +#else > + return false; > +#endif > +} Instead of this, ... > @@ -1369,6 +1370,28 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > #endif > +} > + > +static void riscv_cpu_realize(DeviceState *dev, Error **errp) > +{ > + CPUState *cs = CPU(dev); > + RISCVCPU *cpu = RISCV_CPU(dev); > + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > + Error *local_err = NULL; > + > + cpu_exec_realizefn(cs, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > + if (!riscv_running_kvm()) { ... why not simply do: #ifndef CONFIG_USER_ONLY if (!kvm_enabled()) { > + riscv_cpu_realize_features(dev, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + } #endif ? If riscv_cpu_realize_features() is for all but KVM, then the name isn't ideal.