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[2003:fa:af27:1400:584b:8a9b:5cfa:81e2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47101c21805sm46527655e9.10.2025.10.15.12.13.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Oct 2025 12:13:05 -0700 (PDT) Date: Wed, 15 Oct 2025 19:13:01 +0000 From: Bernhard Beschow To: Thomas Huth , qemu-ppc@nongnu.org CC: qemu-devel@nongnu.org, BALATON Zoltan Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2=5D_hw/ppc/e500=3A_Check_for_compati?= =?US-ASCII?Q?ble_CPU_type_instead_of_aborting_ungracefully?= In-Reply-To: <20251015111243.1585018-1-thuth@redhat.com> References: <20251015111243.1585018-1-thuth@redhat.com> Message-ID: <2E16FBA2-5B65-4606-86DB-DF561338F9E4@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=shentey@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 15=2E Oktober 2025 11:12:43 UTC schrieb Thomas Huth : >From: Thomas Huth > >When using the ppce500 machine with an embedded CPU type that has >the right MMU model, but is not part of the e500 CPU family, QEMU >currently aborts ungracefully: > > $ =2E/qemu-system-ppc -machine ppce500 -cpu e200z5 -nographic > qemu-system-ppc: =2E=2E/qemu/hw/core/gpio=2Ec:108: qdev_get_gpio_in_name= d: > Assertion `n >=3D 0 && n < gpio_list->num_in' failed=2E > Aborted (core dumped) > >The ppce500 machine expects a CPU with certain GPIO interrupt pins, >so let's replace the coarse check for the MMU_BOOKE206 model with >a more precise check that only allows CPUs from the e500 family=2E > >Resolves: https://gitlab=2Ecom/qemu-project/qemu/-/issues/3162 >Signed-off-by: Thomas Huth Thanks for caring, Thomas! Acked-by: Bernhard Beschow >--- > v2: Drop the old check for the MMU_BOOKE206 model > > hw/ppc/e500=2Ec | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > >diff --git a/hw/ppc/e500=2Ec b/hw/ppc/e500=2Ec >index 723c97fad2e=2E=2E3d69428f31c 100644 >--- a/hw/ppc/e500=2Ec >+++ b/hw/ppc/e500=2Ec >@@ -20,6 +20,7 @@ > #include "qemu/guest-random=2Eh" > #include "exec/target_page=2Eh" > #include "qapi/error=2Eh" >+#include "cpu-models=2Eh" > #include "e500=2Eh" > #include "e500-ccsr=2Eh" > #include "net/net=2Eh" >@@ -942,9 +943,8 @@ void ppce500_init(MachineState *machine) > env =3D &cpu->env; > cs =3D CPU(cpu); >=20 >- if (env->mmu_model !=3D POWERPC_MMU_BOOKE206) { >- error_report("MMU model %i not supported by this machine", >- env->mmu_model); >+ if (!(POWERPC_CPU_GET_CLASS(cpu)->svr & POWERPC_SVR_E500)) { >+ error_report("This machine needs a CPU from the e500 family"= ); > exit(1); > } >=20