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[2003:fa:af27:1400:c439:911f:d9f4:5c3c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952d5c9dsm21638098f8f.26.2025.10.28.07.41.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Oct 2025 07:41:37 -0700 (PDT) Date: Tue, 28 Oct 2025 14:41:36 +0000 From: Bernhard Beschow To: Peter Maydell CC: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , =?ISO-8859-1?Q?Phil_Mathieu-Daud=E9?= , Pierrick Bouvier Subject: Re: [PATCH 2/2] hw/arm/imx8mp-evk: Add KVM support In-Reply-To: References: <20250629204851.1778-1-shentey@gmail.com> <20250629204851.1778-3-shentey@gmail.com> Message-ID: <2F14E49B-D152-470C-A87C-525853EB8ED5@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=shentey@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 28=2E Oktober 2025 12:46:34 UTC schrieb Peter Maydell : >On Sun, 29 Jun 2025 at 21:49, Bernhard Beschow wrot= e: >> >> Allows the imx8mp-evk machine to be run with KVM acceleration as a gues= t=2E >> >> Signed-off-by: Bernhard Beschow >> --- >> docs/system/arm/imx8mp-evk=2Erst | 7 +++++++ >> hw/arm/fsl-imx8mp=2Ec | 33 ++++++++++++++++++++++++++++----= - >> hw/arm/imx8mp-evk=2Ec | 11 +++++++++++ >> hw/arm/Kconfig | 3 ++- >> hw/arm/meson=2Ebuild | 2 +- >> 5 files changed, 49 insertions(+), 7 deletions(-) >> >> diff --git a/docs/system/arm/imx8mp-evk=2Erst b/docs/system/arm/imx8mp-= evk=2Erst >> index b2f7d29ade=2E=2E1399820163 100644 >> --- a/docs/system/arm/imx8mp-evk=2Erst >> +++ b/docs/system/arm/imx8mp-evk=2Erst >> @@ -60,3 +60,10 @@ Now that everything is prepared the machine can be s= tarted as follows: >> -dtb imx8mp-evk=2Edtb \ >> -append "root=3D/dev/mmcblk2p2" \ >> -drive file=3Dsdcard=2Eimg,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmc= blk2 >> + >> + >> +KVM Virtualization >> +------------------ >> + >> +To enable hardware-assisted acceleration via KVM, append >> +``-accel kvm -cpu host`` to the command line=2E > >Coming back to this now we've resolved the "does this put >things inside our security-promises that we don't want" >question=2E=2E=2E > >I think we should be a bit clearer in the documentation >about what tradeoffs the user is making here when they select >KVM=2E Specifically: > > * we should note that this is intended only to improve > performance, and is not covered by QEMU's security policy Sure, I'll add it=2E > * we should say that you will not get a Cortex-A53, so any > guest code with tight dependencies on the host CPU type > might not work correctly Ack=2E I'd also hardcode the CPU type to host since asking for a Cortex-A5= 3 always failed on me with KVM=2E > * we should say that the guest will only be able to run > at EL1, and (unlike TCG) there is no EL2 or EL3 Real U-Boot calls back into the on-chip ROM which isn't implemented yet=2E= Furthermore, there are some unimplemented USDHC extensions which prevent c= omplete loading of binaries into RAM by U-Boot (similar limitation exists f= or e500 boards)=2E Therefore the board documentation only advertises direct= kernel boot=2E AFAIU EL2 and EL3 aren't usable there anyway=2E Correct? Do= we need to mention this limitation regardless? > >> diff --git a/hw/arm/fsl-imx8mp=2Ec b/hw/arm/fsl-imx8mp=2Ec >> index 866f4d1d74=2E=2E7e61392abb 100644 >> --- a/hw/arm/fsl-imx8mp=2Ec >> +++ b/hw/arm/fsl-imx8mp=2Ec >> @@ -12,11 +12,13 @@ >> #include "system/address-spaces=2Eh" >> #include "hw/arm/bsa=2Eh" >> #include "hw/arm/fsl-imx8mp=2Eh" >> -#include "hw/intc/arm_gicv3=2Eh" > >Why does this include get removed ? It was used for accessing `TYPE_ARM_GICV3` which has been replaced by `gic= v3_class_name()` whose header is included in fsl-imx8mp=2Eh already=2E > >> #include "hw/misc/unimp=2Eh" >> #include "hw/boards=2Eh" >> +#include "system/kvm=2Eh" >> #include "system/system=2Eh" >> +#include "target/arm/cpu=2Eh" >> #include "target/arm/cpu-qom=2Eh" >> +#include "target/arm/kvm_arm=2Eh" >> #include "qapi/error=2Eh" >> #include "qobject/qlist=2Eh" > >> diff --git a/hw/arm/meson=2Ebuild b/hw/arm/meson=2Ebuild >> index d90be8f4c9=2E=2Ea4212a6ab2 100644 >> --- a/hw/arm/meson=2Ebuild >> +++ b/hw/arm/meson=2Ebuild >> @@ -59,7 +59,7 @@ arm_common_ss=2Eadd(when: 'CONFIG_MUSCA', if_true: fi= les('musca=2Ec')) >> arm_common_ss=2Eadd(when: 'CONFIG_ARMSSE', if_true: files('armsse=2Ec'= )) >> arm_common_ss=2Eadd(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7= =2Ec', 'mcimx7d-sabre=2Ec')) >> arm_common_ss=2Eadd(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx= 8mp=2Ec')) >> -arm_common_ss=2Eadd(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx= 8mp-evk=2Ec')) >> +arm_ss=2Eadd(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk= =2Ec')) >> arm_common_ss=2Eadd(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3= =2Ec')) >> arm_common_ss=2Eadd(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx= 6ul=2Ec', 'mcimx6ul-evk=2Ec')) >> arm_common_ss=2Eadd(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_so= c=2Ec')) > >Philippe, Pierrick: is it OK that this moves the >fsl-imx8p=2Ec file from arm_common to arm_ss, or is there >a preferable way to do this from a single-binary point >of view? Hardcoding to host CPU type in the KVM case might also resolve this issue= =2E Thanks, Bernhard > >thanks >-- PMM