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From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <2a15b7bf-1502-6f95-6b7e-12a2990f5a05@linaro.org>
Date: Tue, 17 Apr 2018 11:58:06 -1000
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Subject: Re: [Qemu-devel] [Qemu-arm] ARM memory barrier patch
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To: Peter Maydell <peter.maydell@linaro.org>, Henry Wertz <hwertz10@gmail.com>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, Richard Henderson <rth@twiddle.net>

On 04/17/2018 11:51 AM, Peter Maydell wrote:
> On 17 April 2018 at 22:32, Henry Wertz <hwertz10@gmail.com> wrote:
>> Please find submitted a patch for ARM memory barriers.  This patch is
>> against qemu-2.12-rc2 but I do believe it should apply for anything from
>> 2.11.x to current. (the code being patched was added in for 2.11 series.)
>>
>>
>> I found with qemu 2.11.x or newer that I would get an illegal instruction
>> error running some Intel binaries on my ARM chromebook.  On investigation,
>> I found it was quitting on memory barriers.
>> qemu instruction:
>> mb $0x31
>> was translating as:
>> 0x604050cc:  5bf07ff5  blpl     #0x600250a8
>>
>> After patch it gives:
>> 0x604050cc:  f57ff05b  dmb      ish
>>
>> In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
>> correct based on online docs, but due to some endian-related shenanigans it
>> had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier
>> for ARMv6) also should be byte swapped  (and this patch does so).
>> I have not checked for correctness of aarch64's barrier instruction.
>>
>> Signed-off-by: Henry Wertz <hwertz10@gmail.com>
> 
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> Richard, did you want to take this via the tcg tree?

Yes, I can do that.


r~