Re: [PATCH v5 03/13] hw/intc: Add hvf vGIC interrupt controller support

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 28/7/25 15:41, Mohamed Mediouni wrote:
> This opens up the door to nested virtualisation support.
> 
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> ---
>   hw/intc/arm_gicv3_hvf.c | 722 ++++++++++++++++++++++++++++++++++++++++
>   hw/intc/meson.build     |   1 +
>   2 files changed, 723 insertions(+)
>   create mode 100644 hw/intc/arm_gicv3_hvf.c


> +static void hvf_gicv3_put_cpu(CPUState *cpu_state, run_on_cpu_data arg)
> +{
> +    uint32_t reg;
> +    uint64_t reg64;
> +    int i, num_pri_bits;
> +
> +    /* Redistributor state */
> +    GICv3CPUState *c = arg.host_ptr;
> +    hv_vcpu_t vcpu = c->cpu->accel->fd;
> +
> +    reg = c->gicr_waker;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, reg);
> +
> +    reg = c->gicr_igroupr0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_IGROUPR0, reg);
> +
> +    reg = ~0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICENABLER0, reg);
> +    reg = c->gicr_ienabler0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISENABLER0, reg);
> +
> +    /* Restore config before pending so we treat level/edge correctly */
> +    reg = half_shuffle32(c->edge_trigger >> 16) << 1;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICFGR1, reg);
> +
> +    reg = ~0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICPENDR0, reg);
> +    reg = c->gicr_ipendr0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISPENDR0, reg);
> +
> +    reg = ~0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0, reg);
> +    reg = c->gicr_iactiver0;
> +    hv_gic_set_redistributor_reg(vcpu, HV_GIC_REDISTRIBUTOR_REG_GICR_ISACTIVER0, reg);
> +
> +    for (i = 0; i < GIC_INTERNAL; i += 4) {
> +        reg = c->gicr_ipriorityr[i] |
> +            (c->gicr_ipriorityr[i + 1] << 8) |
> +            (c->gicr_ipriorityr[i + 2] << 16) |
> +            (c->gicr_ipriorityr[i + 3] << 24);
> +        hv_gic_set_redistributor_reg(vcpu,
> +            HV_GIC_REDISTRIBUTOR_REG_GICR_IPRIORITYR0 + i, reg);
> +    }
> +
> +    /* CPU interface state */
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_SRE_EL1, c->icc_sre_el1);
> +
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_CTLR_EL1,
> +                    c->icc_ctlr_el1[GICV3_NS]);
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN0_EL1,
> +                    c->icc_igrpen[GICV3_G0]);
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_IGRPEN1_EL1,
> +                    c->icc_igrpen[GICV3_G1NS]);
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_PMR_EL1, c->icc_pmr_el1);
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR0_EL1, c->icc_bpr[GICV3_G0]);
> +    hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_BPR1_EL1, c->icc_bpr[GICV3_G1NS]);
> +
> +    num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
> +                    ICC_CTLR_EL1_PRIBITS_MASK) >>
> +                    ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
> +
> +    switch (num_pri_bits) {
> +    case 7:
> +           reg64 = c->icc_apr[GICV3_G0][3];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 3, reg64);
> +        reg64 = c->icc_apr[GICV3_G0][2];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 2, reg64);
> +        /* fall through */
> +    case 6:
> +        reg64 = c->icc_apr[GICV3_G0][1];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1 + 1, reg64);
> +        /* fall through */
> +    default:
> +        reg64 = c->icc_apr[GICV3_G0][0];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP0R0_EL1, reg64);
> +    }
> +
> +    switch (num_pri_bits) {
> +    case 7:
> +        reg64 = c->icc_apr[GICV3_G1NS][3];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 3, reg64);
> +        reg64 = c->icc_apr[GICV3_G1NS][2];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 2, reg64);
> +        /* fall through */
> +    case 6:
> +        reg64 = c->icc_apr[GICV3_G1NS][1];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1 + 1, reg64);
> +        /* fall through */
> +    default:
> +        reg64 = c->icc_apr[GICV3_G1NS][0];
> +        hv_gic_set_icc_reg(vcpu, HV_GIC_ICC_REG_AP1R0_EL1, reg64);
> +    }
> +
> +    if (!hvf_arm_el2_enabled()) {

This method is added in the next patch.

> +        return;
> +    }
> +
> +    hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_VMCR_EL2, c->ich_vmcr_el2);
> +    hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_HCR_EL2, c->ich_hcr_el2);
> +
> +    for (int i = 0; i < GICV3_LR_MAX; i++) {
> +        hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_LR0_EL2, c->ich_lr_el2[i]);
> +    }
> +
> +    num_pri_bits = c->vpribits;
> +
> +    switch (num_pri_bits) {
> +    case 7:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 3,
> +                         c->ich_apr[GICV3_G0][3]);
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 2,
> +                         c->ich_apr[GICV3_G0][2]);
> +      /* fall through */
> +    case 6:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2 + 1,
> +                         c->ich_apr[GICV3_G0][1]);
> +      /* fall through */
> +    default:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP0R0_EL2,
> +                         c->ich_apr[GICV3_G0][0]);
> +    }
> +
> +    switch (num_pri_bits) {
> +    case 7:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 3,
> +                         c->ich_apr[GICV3_G1NS][3]);
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 2,
> +                         c->ich_apr[GICV3_G1NS][2]);
> +      /* fall through */
> +    case 6:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2 + 1,
> +                         c->ich_apr[GICV3_G1NS][1]);
> +      /* fall through */
> +    default:
> +      hv_gic_set_ich_reg(vcpu, HV_GIC_ICH_REG_AP1R0_EL2,
> +                         c->ich_apr[GICV3_G1NS][0]);
> +    }
> +}