[PULL 0/2] qemu-sparc queue 20211121

[PULL 0/2] qemu-sparc queue 20211121

[Mark Cave-Ayland]

The following changes since commit 8627edfb3f1fca24a96a0954148885c3241c10f8:

  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-11-19 17:16:57 +0100)

are available in the Git repository at:

  git://github.com/mcayland/qemu.git tags/qemu-sparc-20211121

for you to fetch changes up to 319e89cdc32096432b578152a47d0d156033b711:

  escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1 (2021-11-21 09:56:52 +0000)

----------------------------------------------------------------
qemu-sparc queue
  - contains fixes for ESCC reset issues with Sun PROM and OpenBSD on SPARC32

----------------------------------------------------------------
Mark Cave-Ayland (2):
      escc: always set STATUS_TXEMPTY in R_STATUS on device reset
      escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1

 hw/char/escc.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

[PULL 1/2] escc: always set STATUS_TXEMPTY in R_STATUS on device reset

[Mark Cave-Ayland]

The "Transmit Interrupts and Transmit Buffer Empty Bit" section of the ESCC
datasheet states the following about the STATUS_TXEMPTY bit: "After a hardware
reset (including a hardware reset by software), or a channel reset, this bit
is set to 1".

Update escc_reset() to set the STATUS_TXEMPTY bit in the R_STATUS register
on device reset as described which fixes a regression whereby the Sun PROM
checks this bit early on startup and gets stuck in an infinite loop if it is
not set.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20211118181835.18497-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/escc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/char/escc.c b/hw/char/escc.c
index 0fce4f6324..a7d9050c83 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -354,6 +354,17 @@ static void escc_reset(DeviceState *d)
             cs->rregs[j] = 0;
             cs->wregs[j] = 0;
         }
+
+        /*
+         * ...but there is an exception. The "Transmit Interrupts and Transmit
+         * Buffer Empty Bit" section on page 50 of the ESCC datasheet says of
+         * the STATUS_TXEMPTY bit in R_STATUS: "After a hardware reset
+         * (including a hardware reset by software), or a channel reset, this
+         * bit is set to 1". The Sun PROM checks this bit early on startup and
+         * gets stuck in an infinite loop if it is not set.
+         */
+        cs->rregs[R_STATUS] |= STATUS_TXEMPTY;
+
         escc_reset_chn(cs);
     }
 }
-- 
2.20.1

[PULL 2/2] escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1

[Mark Cave-Ayland]

The ESCC datasheet states that SPEC_ALLSENT is always set in sync mode and set
in async mode once all characters have cleared the transmitter. Since writes to
SERIAL_DATA use a synchronous chardev API, the guest can never see the state when
transmission is in progress so it is possible to set SPEC_ALLSENT in the
R_SPEC register unconditionally.

This fixes a hang when using the Sun PROM as it attempts to enumerate the
onboard serial devices, and a similar hang in OpenBSD SPARC32 where in both cases
the boot process will not proceed until SPEC_ALLSENT has been set after writing
to W_TXCTRL1.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20211118181835.18497-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/char/escc.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/char/escc.c b/hw/char/escc.c
index a7d9050c83..8755d8d34f 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -586,6 +586,20 @@ static void escc_mem_write(void *opaque, hwaddr addr,
             s->wregs[s->reg] = val;
             break;
         case W_TXCTRL1:
+            s->wregs[s->reg] = val;
+            /*
+             * The ESCC datasheet states that SPEC_ALLSENT is always set in
+             * sync mode, and set in async mode when all characters have
+             * cleared the transmitter. Since writes to SERIAL_DATA use the
+             * blocking qemu_chr_fe_write_all() function to write each
+             * character, the guest can never see the state when async data
+             * is in the process of being transmitted so we can set this bit
+             * unconditionally regardless of the state of the W_TXCTRL1 mode
+             * bits.
+             */
+            s->rregs[R_SPEC] |= SPEC_ALLSENT;
+            escc_update_parameters(s);
+            break;
         case W_TXCTRL2:
             s->wregs[s->reg] = val;
             escc_update_parameters(s);
-- 
2.20.1

Re: [PULL 0/2] qemu-sparc queue 20211121

[Richard Henderson]

On 11/21/21 10:59 AM, Mark Cave-Ayland wrote:
> The following changes since commit 8627edfb3f1fca24a96a0954148885c3241c10f8:
> 
>    Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-11-19 17:16:57 +0100)
> 
> are available in the Git repository at:
> 
>    git://github.com/mcayland/qemu.git tags/qemu-sparc-20211121
> 
> for you to fetch changes up to 319e89cdc32096432b578152a47d0d156033b711:
> 
>    escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1 (2021-11-21 09:56:52 +0000)
> 
> ----------------------------------------------------------------
> qemu-sparc queue
>    - contains fixes for ESCC reset issues with Sun PROM and OpenBSD on SPARC32
> 
> ----------------------------------------------------------------
> Mark Cave-Ayland (2):
>        escc: always set STATUS_TXEMPTY in R_STATUS on device reset
>        escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1
> 
>   hw/char/escc.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)

Applied, thanks.

r~