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From: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
To: Thomas Huth <thuth@redhat.com>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
	"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
	"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
	"philmd@linaro.org" <philmd@linaro.org>,
	"alistair23@gmail.com" <alistair23@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v11 13/13] test/functional: Add test for boston-aia board
Date: Wed, 15 Oct 2025 13:04:49 +0000	[thread overview]
Message-ID: <2a3f6bc1-fe2b-4fa9-a81f-75b6517cf866@htecgroup.com> (raw)
In-Reply-To: <b55bb00b-4f2a-471c-9be2-a8f736e7af6a@redhat.com>


On 15. 10. 25. 14:41, Thomas Huth wrote:
> CAUTION: This email originated from outside of the organization. Do 
> not click links or open attachments unless you recognize the sender 
> and know the content is safe.
>
>
> On 15/10/2025 13.58, Djordje Todorovic wrote:
>> Add functional test for Boston AIA board. The P8700 RISC-V based
>> CPU by MIPS supports it at the moment.
>>
>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>>   tests/functional/riscv64/meson.build          |   2 +
>>   .../functional/riscv64/test_riscv64_boston.py | 124 ++++++++++++++++++
>>   2 files changed, 126 insertions(+)
>>   create mode 100755 tests/functional/riscv64/test_riscv64_boston.py
>>
>> diff --git a/tests/functional/riscv64/meson.build 
>> b/tests/functional/riscv64/meson.build
>> index c1704d9275..58d541f8c2 100644
>> --- a/tests/functional/riscv64/meson.build
>> +++ b/tests/functional/riscv64/meson.build
>> @@ -1,12 +1,14 @@
>>   # SPDX-License-Identifier: GPL-2.0-or-later
>>
>>   test_riscv64_timeouts = {
>> +  'riscv64_boston' : 120,
>>     'tuxrun' : 120,
>>   }
>>
>>   tests_riscv64_system_quick = [
>>     'migration',
>>     'opensbi',
>> +  'riscv64_boston',
>>   ]
>>
>>   tests_riscv64_system_thorough = [
>> diff --git a/tests/functional/riscv64/test_riscv64_boston.py 
>> b/tests/functional/riscv64/test_riscv64_boston.py
>> new file mode 100755
>> index 0000000000..d450f7eaf5
>> --- /dev/null
>> +++ b/tests/functional/riscv64/test_riscv64_boston.py
>
> In case you respin: Please drop the "riscv64" in the file name. Since the
> tests are now stored in a "riscv64" folder, the target name in the 
> file name
> is not necessary anymore.
>
>> @@ -0,0 +1,124 @@
>> +#!/usr/bin/env python3
>> +#
>> +# Boston board test for RISC-V P8700 processor by MIPS
>> +#
>> +# Copyright (c) 2025 MIPS
>> +#
>> +# SPDX-License-Identifier: GPL-2.0-or-later
>> +#
>> +
>> +import os
>
> "import os" seems to be unused, I think you could drop it.
>
> Apart from that, the test looks fine to me now, thanks!
>
>  Thomas
>

Hi Thomas,

Thanks a lot for your review!
I am addressing this in v12.

Best,
Djordje


>> +from qemu_test import QemuSystemTest, Asset
>> +from qemu_test import wait_for_console_pattern
>> +
>> +
>> +class RiscvBostonTest(QemuSystemTest):
>> +    """
>> +    Test the boston-aia board with P8700 processor
>> +    """
>> +
>> +    ASSET_FW_PAYLOAD = Asset(
>> + 
>> 'https://github.com/MIPS/linux-test-downloads/raw/main/p8700/fw_payload.bin',
>> + 'd6f4ae14d0c178c1d0bb38ddf64557536ca8602a588b220729a8aa17caa383aa')
>> +
>> +    ASSET_ROOTFS = Asset(
>> + 
>> 'https://github.com/MIPS/linux-test-downloads/raw/main/p8700/rootfs.ext2',
>> + 'f937e21b588f0d1d17d10a063053979686897bbbbc5e9617a5582f7c1f48e565')
>> +
>> +    def _boot_linux_test(self, smp_count):
>> +        """Common setup and boot test for Linux on Boston board
>> +
>> +        Args:
>> +            smp_count: Number of CPUs to use for SMP
>> +        """
>> +        self.set_machine('boston-aia')
>> +        fw_payload_path = self.ASSET_FW_PAYLOAD.fetch()
>> +        rootfs_path = self.ASSET_ROOTFS.fetch()
>> +
>> +        self.vm.add_args('-cpu', 'mips-p8700')
>> +        self.vm.add_args('-m', '2G')
>> +        self.vm.add_args('-smp', str(smp_count))
>> +        self.vm.add_args('-kernel', fw_payload_path)
>> +        self.vm.add_args('-drive', 
>> f'file={rootfs_path},format=raw,snapshot=on')
>> +
>> +        self.vm.set_console()
>> +        self.vm.launch()
>> +
>> +        # Wait for OpenSBI
>> +        wait_for_console_pattern(self, 'OpenSBI')
>> +
>> +        # Wait for Linux kernel boot
>> +        wait_for_console_pattern(self, 'Linux version')
>> +        wait_for_console_pattern(self, 'Machine model: MIPS P8700')
>> +
>> +        # Test e1000e network card functionality
>> +        wait_for_console_pattern(self, 'e1000e')
>> +        wait_for_console_pattern(self, 'Network Connection')
>> +
>> +        # Wait for boot to complete - system reaches login prompt
>> +        wait_for_console_pattern(self, 'Run /sbin/init as init 
>> process')
>> +
>> +    def test_boston_boot_linux_min_cpus(self):
>> +        """
>> +        Test Linux kernel boot with minimum CPU count (2)
>> +        """
>> +        self._boot_linux_test(smp_count=2)
>> +
>> +    def test_boston_boot_linux_7_cpus(self):
>> +        """
>> +        Test Linux kernel boot with 7 CPUs
>> +
>> +        7 CPUs is a special configuration that tests odd CPU count
>> +        handling and ensures proper core distribution across clusters.
>> +        """
>> +        self._boot_linux_test(smp_count=7)
>> +
>> +    def test_boston_boot_linux_35_cpus(self):
>> +        """
>> +        Test Linux kernel boot with 35 CPUs
>> +
>> +        35 CPUs is a special configuration that tests a non-power-of-2
>> +        CPU count above 32, validating proper handling of larger
>> +        asymmetric SMP configurations.
>> +        """
>> +        self._boot_linux_test(smp_count=35)
>> +
>> +    def test_boston_boot_linux_max_cpus(self):
>> +        """
>> +        Test Linux kernel boot with maximum supported CPU count (64)
>> +        """
>> +        self._boot_linux_test(smp_count=64)
>> +
>> +    def test_boston_invalid_cpu_count(self):
>> +        """
>> +        Test that 65 CPUs is rejected as invalid (negative test case)
>> +        """
>> +        from subprocess import run, PIPE
>> +
>> +        fw_payload_path = self.ASSET_FW_PAYLOAD.fetch()
>> +        rootfs_path = self.ASSET_ROOTFS.fetch()
>> +
>> +        cmd = [
>> +            self.qemu_bin,
>> +            '-M', 'boston-aia',
>> +            '-cpu', 'mips-p8700',
>> +            '-m', '2G',
>> +            '-smp', '65',
>> +            '-kernel', fw_payload_path,
>> +            '-drive', f'file={rootfs_path},format=raw,snapshot=on',
>> +            '-nographic'
>> +        ]
>> +
>> +        # Run QEMU and expect it to fail immediately.
>> +        result = run(cmd, capture_output=True, text=True, timeout=5)
>> +
>> +        # Check that QEMU exited with error code 1
>> +        self.assertEqual(result.returncode, 1,
>> +                         "QEMU should exit with code 1 for invalid 
>> SMP count")
>> +
>> +        # Check error message
>> +        self.assertIn('Invalid SMP CPUs 65', result.stderr,
>> +                      "Error message should indicate invalid SMP CPU 
>> count")
>> +
>> +if __name__ == '__main__':
>> +    QemuSystemTest.main()
>

      reply	other threads:[~2025-10-15 13:06 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15 11:58 [PATCH v11 00/13] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 03/13] target/riscv: Add " Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 02/13] target/riscv: Add cpu_set_exception_base Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 01/13] hw/intc: Allow gaps in hartids for aclint and aplic Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 05/13] target/riscv: Add mips.ccmov instruction Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 04/13] target/riscv: Add MIPS P8700 CSRs Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 06/13] target/riscv: Add mips.pref instruction Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 08/13] hw/misc: Add RISC-V CMGCR device implementation Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 07/13] target/riscv: Add Xmipslsp instructions Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 10/13] hw/riscv: Add support for RISCV CPS Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 09/13] hw/misc: Add RISC-V CPC device implementation Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 11/13] hw/riscv: Add support for MIPS Boston-aia board mode Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 12/13] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 Djordje Todorovic
2025-10-15 11:58 ` [PATCH v11 13/13] test/functional: Add test for boston-aia board Djordje Todorovic
2025-10-15 12:41   ` Thomas Huth
2025-10-15 13:04     ` Djordje Todorovic [this message]

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