From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 5/6] target/arm: Add ID_ISAR6
Date: Fri, 29 Jun 2018 07:47:45 -0700 [thread overview]
Message-ID: <2aadcec2-e73e-baba-1851-b7894c561999@linaro.org> (raw)
In-Reply-To: <CAFEAcA8zTOm6eesQVF_1_VY=JsVGpvoWstBwfL32ggARPPzOnQ@mail.gmail.com>
On 06/29/2018 01:40 AM, Peter Maydell wrote:
>> cpu->id_isar5 = 0x00000000;
>> + cpu->id_isar6 = 0x00000000;
...
>> cpu->id_isar5 = 0x00000000;
>> + cpu->id_isar6 = 0x00000000;
...
>> cpu->id_isar5 = 0x00000000;
>> + cpu->id_isar6 = 0x00000000;
...
>> cpu->id_isar5 = 0x0;
>> + cpu->id_isar6 = 0x0;
...
> The ARMCPU struct fields should all be initially cleared to
> zero, so you don't really need to explicitly zero-initialize
> isar6 all over the place like this. (Compare isar5, which is
> I think only set in CPUs that are new enough that their TRMs
> mentioned it.)
Actually, the fact that isar5 is explicitly set to 0
in many places is the reason that I initialize isar6.
r~
next prev parent reply other threads:[~2018-06-29 14:47 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-29 0:15 [Qemu-devel] [PATCH 0/6] target/arm SVE updates Richard Henderson
2018-06-29 0:15 ` [Qemu-devel] [PATCH 1/6] target/arm: Fix SVE signed division vs x86 overflow exception Richard Henderson
2018-06-29 0:42 ` Philippe Mathieu-Daudé
2018-06-29 8:29 ` Peter Maydell
2018-06-29 9:10 ` Peter Maydell
2018-06-29 14:43 ` Richard Henderson
2018-06-29 0:15 ` [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks Richard Henderson
2018-06-29 0:48 ` Philippe Mathieu-Daudé
2018-06-29 8:30 ` Peter Maydell
2018-06-29 9:23 ` Laurent Desnogues
2018-06-29 0:15 ` [Qemu-devel] [PATCH 3/6] target/arm: Prune a57 features from max Richard Henderson
2018-06-29 0:38 ` Philippe Mathieu-Daudé
2018-06-29 8:31 ` Peter Maydell
2018-06-29 0:15 ` [Qemu-devel] [PATCH 4/6] target/arm: Prune a15 " Richard Henderson
2018-06-29 0:39 ` Philippe Mathieu-Daudé
2018-06-29 8:32 ` Peter Maydell
2018-06-29 0:15 ` [Qemu-devel] [PATCH 5/6] target/arm: Add ID_ISAR6 Richard Henderson
2018-06-29 0:57 ` Philippe Mathieu-Daudé
2018-06-29 1:09 ` Philippe Mathieu-Daudé
2018-06-29 3:51 ` Richard Henderson
2018-06-29 8:40 ` Peter Maydell
2018-06-29 14:47 ` Richard Henderson [this message]
2018-06-29 0:15 ` [Qemu-devel] [PATCH 6/6] target/arm: Set ISAR bits for -cpu max Richard Henderson
2018-06-29 1:03 ` Philippe Mathieu-Daudé
2018-06-29 8:42 ` Peter Maydell
2018-06-29 14:54 ` Richard Henderson
2018-06-29 15:08 ` Peter Maydell
2018-06-29 1:06 ` [Qemu-devel] [PATCH 0/6] target/arm SVE updates Philippe Mathieu-Daudé
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