From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CfpgS-0006ti-TZ for qemu-devel@nongnu.org; Sat, 18 Dec 2004 20:16:28 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1CfpgS-0006tO-7G for qemu-devel@nongnu.org; Sat, 18 Dec 2004 20:16:28 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CfpgS-0006tE-2w for qemu-devel@nongnu.org; Sat, 18 Dec 2004 20:16:28 -0500 Received: from [64.233.170.202] (helo=rproxy.gmail.com) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CfpVq-0008Sa-3L for qemu-devel@nongnu.org; Sat, 18 Dec 2004 20:05:30 -0500 Received: by rproxy.gmail.com with SMTP id y7so106803rne for ; Sat, 18 Dec 2004 17:05:26 -0800 (PST) Message-ID: <2ad73a041218170567573ad@mail.gmail.com> Date: Sat, 18 Dec 2004 23:05:25 -0200 From: =?ISO-8859-1?Q?Andr=E9_Braga?= Subject: Re: [Qemu-devel] SMB for DOS ? In-Reply-To: <1103402896.21894.66.camel@aragorn> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit References: <41C20E6A.7010507@bellard.org> <03BFD3A6-4FBC-11D9-8729-00039307264A@stanfordalumni.org> <20041218181323.GB8020@mail.13thfloor.at> <200412181832.24252.paul@codesourcery.com> <1103402896.21894.66.camel@aragorn> Reply-To: =?ISO-8859-1?Q?Andr=E9_Braga?= , qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, 18 Dec 2004 12:48:16 -0800, John R. Hogerhuis wrote: > This raises an interesting question in my mind, given the existence of > "reconfigurable computing" where you have a PCI card containing an FPGA > loaded onto your machine (such things do exist, and I expect in the > future to start seeing these things standard on motherboards). Certainly > an MMU can be created in FPGA code. There is an interesting article on > reconfigurable computing in this month's Linux Journal, btw. The PCI bus is still too slow to handle such tasks efficiently. Maybe if the FPGA could be tied to the north bridge it would be actually useful, or maybe the PCI Express bus is up to the task; anyway, the current implementations wouldn't be that helpful at all. The FPGA accelerators use to have many small "computing elements" and some decent amount of local RAM. Going back and forth in the PCI bus would kill most performance gains one would expect. -- "The user-friendly computer is a red herring. The user-friendliness of a book just makes it easier to turn pages. There's nothing user-friendly about learning to read." -- Alan Kay