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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id j13sm17966922wru.86.2020.10.10.11.49.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Oct 2020 11:49:16 -0700 (PDT) Subject: Re: [PATCH v2 18/20] hw/mips/malta: Set CPU frequency to 320 MHz To: qemu-devel@nongnu.org References: <20201010172617.3079633-1-f4bug@amsat.org> <20201010172617.3079633-19-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <2b2e8f70-a0a8-7408-3d7e-1661de3d8d49@amsat.org> Date: Sat, 10 Oct 2020 20:49:14 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 MIME-Version: 1.0 In-Reply-To: <20201010172617.3079633-19-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.207, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Huacai Chen , Aleksandar Rikalo , Luc Michel , Paul Burton , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Huacai Chen , Paolo Bonzini , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/10/20 7:26 PM, Philippe Mathieu-Daudé wrote: > The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create > a 'cpuclk' output clock and connect it to the CPU input clock. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/mips/malta.c | 20 +++++++++++++++++--- > 1 file changed, 17 insertions(+), 3 deletions(-) > > diff --git a/hw/mips/malta.c b/hw/mips/malta.c > index 4019c9dc1a8..c1e8fceeea7 100644 > --- a/hw/mips/malta.c > +++ b/hw/mips/malta.c > @@ -57,6 +57,7 @@ > #include "sysemu/kvm.h" > #include "hw/semihosting/semihost.h" > #include "hw/mips/cps.h" > +#include "hw/qdev-clock.h" > > #define ENVP_ADDR 0x80002000l > #define ENVP_NB_ENTRIES 16 > @@ -94,6 +95,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) > struct MaltaState { > SysBusDevice parent_obj; > > + Clock *cpuclk; > MIPSCPSState cps; > qemu_irq i8259[ISA_NUM_IRQS]; > }; > @@ -1159,7 +1161,7 @@ static void main_cpu_reset(void *opaque) > } > } > > -static void create_cpu_without_cps(MachineState *ms, > +static void create_cpu_without_cps(MachineState *ms, MaltaState *s, > qemu_irq *cbus_irq, qemu_irq *i8259_irq) > { > CPUMIPSState *env; > @@ -1167,7 +1169,9 @@ static void create_cpu_without_cps(MachineState *ms, > int i; > > for (i = 0; i < ms->smp.cpus; i++) { > - cpu = MIPS_CPU(cpu_create(ms->cpu_type)); > + cpu = MIPS_CPU(object_new(ms->cpu_type)); > + qdev_connect_clock_in(DEVICE(cpu), "clk", s->cpuclk); I forgot to rename this "clk-in" :( > + qdev_realize(DEVICE(cpu), NULL, &error_abort); > > /* Init internal devices */ > cpu_mips_irq_init_cpu(cpu); > @@ -1189,6 +1193,7 @@ static void create_cps(MachineState *ms, MaltaState *s, > &error_fatal); > object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, > &error_fatal); > + qdev_connect_clock_in(DEVICE(&s->cps), "clk", s->cpuclk); > sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); > > sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); > @@ -1203,7 +1208,7 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s, > if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { > create_cps(ms, s, cbus_irq, i8259_irq); > } else { > - create_cpu_without_cps(ms, cbus_irq, i8259_irq); > + create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); > } > } > > @@ -1421,10 +1426,19 @@ void mips_malta_init(MachineState *machine) > pci_vga_init(pci_bus); > } > > +static void mips_malta_instance_init(Object *obj) > +{ > + MaltaState *s = MIPS_MALTA(obj); > + > + s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpuclk-out"); > + clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ > +} > + > static const TypeInfo mips_malta_device = { > .name = TYPE_MIPS_MALTA, > .parent = TYPE_SYS_BUS_DEVICE, > .instance_size = sizeof(MaltaState), > + .instance_init = mips_malta_instance_init, > }; > > static void mips_malta_machine_init(MachineClass *mc) >