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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af56ea947afsm9656324a12.71.2025.03.18.15.45.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Mar 2025 15:45:44 -0700 (PDT) Message-ID: <2b438e13-b377-4b4e-a4ff-0b219d7f3964@linaro.org> Date: Tue, 18 Mar 2025 15:45:42 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/13] target/arm/cpu: define same set of registers for aarch32 and aarch64 To: Pierrick Bouvier , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , qemu-arm@nongnu.org, alex.bennee@linaro.org, Peter Maydell , kvm@vger.kernel.org, Paolo Bonzini , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= References: <20250318045125.759259-1-pierrick.bouvier@linaro.org> <20250318045125.759259-11-pierrick.bouvier@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250318045125.759259-11-pierrick.bouvier@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/17/25 21:51, Pierrick Bouvier wrote: > To eliminate TARGET_AARCH64, we need to make various definitions common > between 32 and 64 bit Arm targets. > Added registers are used only by aarch64 code, and the only impact is on > the size of CPUARMState, and added zarray > (ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB) > > It could be eventually possible to allocate this array only for aarch64 > emulation, but I'm not sure it's worth the hassle to save a few KB per > vcpu. Running qemu-system takes already several hundreds of MB of > (resident) memory, and qemu-user takes dozens of MB of (resident) memory > anyway. > > Signed-off-by: Pierrick Bouvier > --- > target/arm/cpu.h | 6 ------ > 1 file changed, 6 deletions(-) Reviewed-by: Richard Henderson I think this could easily squash with ARM_MAX_VQ, since the rationale is better spelled out here. r~