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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	alistair23@gmail.com, chihmin.chao@sifive.com,
	palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
	linux-csky@vger.kernel.org, wxy194768@alibaba-inc.com,
	qemu-devel@nongnu.org
Subject: Re: [PATCH v4 4/5] target/riscv: add fault-only-first unit stride load
Date: Thu, 27 Feb 2020 12:03:53 -0800	[thread overview]
Message-ID: <2b7d7af1-61ee-edf6-5e57-1108428f920c@linaro.org> (raw)
In-Reply-To: <20200225103508.7651-5-zhiwei_liu@c-sky.com>

On 2/25/20 2:35 AM, LIU Zhiwei wrote:
> +GEN_VEXT_LD_ELEM(vlbff_v_b, int8_t,  int8_t,  H1, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_h, int8_t,  int16_t, H2, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_w, int8_t,  int32_t, H4, ldsb)
> +GEN_VEXT_LD_ELEM(vlbff_v_d, int8_t,  int64_t, H8, ldsb)
> +GEN_VEXT_LD_ELEM(vlhff_v_h, int16_t, int16_t, H2, ldsw)
> +GEN_VEXT_LD_ELEM(vlhff_v_w, int16_t, int32_t, H4, ldsw)
> +GEN_VEXT_LD_ELEM(vlhff_v_d, int16_t, int64_t, H8, ldsw)
> +GEN_VEXT_LD_ELEM(vlwff_v_w, int32_t, int32_t, H4, ldl)
> +GEN_VEXT_LD_ELEM(vlwff_v_d, int32_t, int64_t, H8, ldl)
> +GEN_VEXT_LD_ELEM(vleff_v_b, int8_t,  int8_t,  H1, ldsb)
> +GEN_VEXT_LD_ELEM(vleff_v_h, int16_t, int16_t, H2, ldsw)
> +GEN_VEXT_LD_ELEM(vleff_v_w, int32_t, int32_t, H4, ldl)
> +GEN_VEXT_LD_ELEM(vleff_v_d, int64_t, int64_t, H8, ldq)
> +GEN_VEXT_LD_ELEM(vlbuff_v_b, uint8_t,  uint8_t,  H1, ldub)
> +GEN_VEXT_LD_ELEM(vlbuff_v_h, uint8_t,  uint16_t, H2, ldub)
> +GEN_VEXT_LD_ELEM(vlbuff_v_w, uint8_t,  uint32_t, H4, ldub)
> +GEN_VEXT_LD_ELEM(vlbuff_v_d, uint8_t,  uint64_t, H8, ldub)
> +GEN_VEXT_LD_ELEM(vlhuff_v_h, uint16_t, uint16_t, H2, lduw)
> +GEN_VEXT_LD_ELEM(vlhuff_v_w, uint16_t, uint32_t, H4, lduw)
> +GEN_VEXT_LD_ELEM(vlhuff_v_d, uint16_t, uint64_t, H8, lduw)
> +GEN_VEXT_LD_ELEM(vlwuff_v_w, uint32_t, uint32_t, H4, ldl)
> +GEN_VEXT_LD_ELEM(vlwuff_v_d, uint32_t, uint64_t, H8, ldl)

We definitely should not have a 3rd copy of these.


> +        if (i == 0) {
> +            probe_read_access(env, addr, nf * msz, ra);
> +        } else {
> +            /* if it triggles an exception, no need to check watchpoint */

triggers.

> +            offset = -(addr | TARGET_PAGE_MASK);
> +            remain = nf * msz;
> +            while (remain > 0) {
> +                host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmuidx);
> +                if (host) {
> +#ifdef CONFIG_USER_ONLY
> +                    if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
> +                        vl = i;
> +                        goto ProbeSuccess;
> +                    }
> +#else
> +                    probe_read_access(env, addr, nf * msz, ra);
> +#endif

Good job finding all of the corner cases.  I should invent a new cputlb
function that handles this better.  For now, this is the best we can do.


r~


  reply	other threads:[~2020-02-27 20:04 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-25 10:35 [PATCH v4 0/5] target/riscv: support vector extension part 2 LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions LIU Zhiwei
2020-02-27 19:17   ` Richard Henderson
2020-02-28  1:50     ` LIU Zhiwei
2020-02-28  3:33       ` Richard Henderson
2020-02-28  6:16         ` LIU Zhiwei
2020-03-07  4:36     ` LIU Zhiwei
2020-03-07 17:44       ` Richard Henderson
2020-02-25 10:35 ` [PATCH v4 2/5] target/riscv: add vector " LIU Zhiwei
2020-02-27 19:36   ` Richard Henderson
2020-02-28  2:11     ` LIU Zhiwei
2020-03-07  4:29     ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 3/5] target/riscv: add vector index " LIU Zhiwei
2020-02-27 19:49   ` Richard Henderson
2020-02-28  2:13     ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 4/5] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-02-27 20:03   ` Richard Henderson [this message]
2020-02-28  2:17     ` LIU Zhiwei
2020-02-25 10:35 ` [PATCH v4 5/5] target/riscv: add vector amo operations LIU Zhiwei
2020-02-28  5:38   ` Richard Henderson
2020-02-28  9:19     ` LIU Zhiwei
2020-02-28 18:46       ` Richard Henderson
2020-02-29 13:16         ` LIU Zhiwei

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