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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bernhard Beschow <shentey@gmail.com>, qemu-devel@nongnu.org
Cc: Eduardo Habkost <eduardo@habkost.net>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Sergio Lopez <slp@redhat.com>, Ani Sinha <anisinha@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Igor Mammedov <imammedo@redhat.com>
Subject: Re: [PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately
Date: Mon, 28 Aug 2023 14:08:58 +0200	[thread overview]
Message-ID: <2b82a710-1d02-ec1f-c7b2-b9ebce77c496@linaro.org> (raw)
In-Reply-To: <20230828073609.5710-9-shentey@gmail.com>

On 28/8/23 09:36, Bernhard Beschow wrote:
> The bit positions of both registers are related. Tracing the registers
> independently results in the same offsets across these registers which
> eases debugging.
> 
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
>   hw/acpi/core.c       | 10 +++++++---
>   hw/acpi/trace-events |  6 ++++--
>   2 files changed, 11 insertions(+), 5 deletions(-)


> diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events
> index 159937ddb9..d387adfb0b 100644
> --- a/hw/acpi/trace-events
> +++ b/hw/acpi/trace-events
> @@ -18,8 +18,10 @@ mhp_acpi_pc_dimm_deleted(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm deleted"
>   mhp_acpi_pc_dimm_delete_failed(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm delete failed"
>   
>   # core.c
> -acpi_gpe_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 0x%" PRIx8
> -acpi_gpe_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 0x%" PRIx8
> +acpi_gpe_sts_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 0x%" PRIx8
> +acpi_gpe_en_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 0x%" PRIx8
> +acpi_gpe_sts_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 0x%" PRIx8
> +acpi_gpe_en_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 0x%" PRIx8

0x%02 for val? Otherwise:

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



      reply	other threads:[~2023-08-28 12:09 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28  7:36 [PATCH 0/8] ACPI: X86 AML generation and GPE tracing cleanup Bernhard Beschow
2023-08-28  7:36 ` [PATCH 1/8] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly Bernhard Beschow
2023-08-28 12:11   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 2/8] hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback Bernhard Beschow
2023-08-28 12:02   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 3/8] hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method Bernhard Beschow
2023-08-28 12:03   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 4/8] hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h" Bernhard Beschow
2023-08-28 12:04   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 5/8] hw/i386: Remove now redundant TYPE_ACPI_GED_X86 Bernhard Beschow
2023-08-28 12:05   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 6/8] hw/i386/acpi-build: Determine SMI command port just once Bernhard Beschow
2023-08-28 12:10   ` Philippe Mathieu-Daudé
2023-08-28  7:36 ` [PATCH 7/8] hw/acpi: Trace GPE access in all device models, not just PIIX4 Bernhard Beschow
2023-08-28  7:36 ` [PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately Bernhard Beschow
2023-08-28 12:08   ` Philippe Mathieu-Daudé [this message]

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