* [PATCH v3 00/33] single-binary: compile target/arm twice
@ 2025-05-01 6:23 Pierrick Bouvier
2025-05-01 6:23 ` [PATCH v3 01/33] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint Pierrick Bouvier
` (32 more replies)
0 siblings, 33 replies; 79+ messages in thread
From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee,
Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm,
Pierrick Bouvier
More work toward single-binary.
Some files have external dependencies for the single-binary:
- target/arm/machine.c: migration
- target/arm/gdbstub.c: gdbhelpers
- target/arm/arm-qmp-cmds.c: qapi
They will not be ported in this series.
Built on {linux, windows, macos} x {x86_64, aarch64}
Fully tested on linux-x86_64
v1
--
- target/arm/cpu.c
v2
--
- Remove duplication of kvm struct and constant (Alex)
- Use target_big_endian() (Anton)
v3
--
CI: https://github.com/pbo-linaro/qemu/actions/runs/14765763846/job/41456754153
- Add missing license for new files (Richard)
- target/arm/debug_helper.c
- target/arm/helper.c
- target/arm/vfp_fpscr.c
- target/arm/arch_dump.c
- target/arm/arm-powerctl.c
- target/arm/cortex-regs.c
- target/arm/ptw.c
- target/arm/kvm-stub.c
Philippe Mathieu-Daudé (1):
target/arm: Replace target_ulong -> uint64_t for HWBreakpoint
Pierrick Bouvier (32):
include/system/hvf: missing vaddr include
meson: add common libs for target and target_system
target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h
target/arm/kvm-stub: add kvm_arm_reset_vcpu stub
target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c
accel/hvf: add hvf_enabled() for common code
target/arm/cpu: remove TARGET_BIG_ENDIAN dependency
target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state
common
target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features
target/arm/cpu: compile file twice (user, system) only
target/arm/cpu32-stubs.c: compile file twice (user, system)
target/arm/helper: use i64 for exception_pc_alignment
target/arm/helper: user i64 for probe_access
target/arm/helper: extract common helpers
target/arm/debug_helper: only include common helpers
target/arm/debug_helper: remove target_ulong
target/arm/debug_helper: compile file twice (user, system)
target/arm/helper: restrict include to common helpers
target/arm/helper: replace target_ulong by vaddr
target/arm/helper: expose aarch64 cpu registration
target/arm/helper: remove remaining TARGET_AARCH64
target/arm/helper: compile file twice (user, system)
target/arm/vfp_fpscr: compile file twice (user, system)
target/arm/arch_dump: remove TARGET_AARCH64 conditionals
target/arm/arch_dump: compile file once (system)
target/arm/arm-powerctl: compile file once (system)
target/arm/cortex-regs: compile file once (system)
target/arm/ptw: replace target_ulong with uint64_t
target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw
target/arm/ptw: compile file once (system)
target/arm/meson: accelerator files are not needed in user mode
target/arm/kvm-stub: compile file once (system)
meson.build | 78 ++-
include/system/hvf.h | 15 +-
target/arm/helper.h | 1152 +------------------------------
target/arm/internals.h | 6 +-
target/arm/kvm_arm.h | 83 +--
target/arm/tcg/helper.h | 1153 ++++++++++++++++++++++++++++++++
accel/hvf/hvf-stub.c | 5 +
target/arm/arch_dump.c | 6 -
target/arm/cpu.c | 47 +-
target/arm/cpu32-stubs.c | 26 +
target/arm/debug_helper.c | 6 +-
target/arm/helper.c | 21 +-
target/arm/hyp_gdbstub.c | 6 +-
target/arm/kvm-stub.c | 87 +++
target/arm/kvm.c | 29 +
target/arm/ptw.c | 17 +-
target/arm/tcg/op_helper.c | 2 +-
target/arm/tcg/tlb_helper.c | 2 +-
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate.c | 2 +-
accel/hvf/meson.build | 1 +
target/arm/meson.build | 43 +-
22 files changed, 1436 insertions(+), 1353 deletions(-)
create mode 100644 target/arm/tcg/helper.h
create mode 100644 accel/hvf/hvf-stub.c
create mode 100644 target/arm/cpu32-stubs.c
--
2.47.2
^ permalink raw reply [flat|nested] 79+ messages in thread* [PATCH v3 01/33] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 02/33] include/system/hvf: missing vaddr include Pierrick Bouvier ` (31 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier From: Philippe Mathieu-Daudé <philmd@linaro.org> CPUARMState::pc is of type uint64_t. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/internals.h | 6 +++--- target/arm/hyp_gdbstub.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffebd..c30689c9fcd 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1949,9 +1949,9 @@ extern GArray *hw_breakpoints, *hw_watchpoints; #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i)) #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i)) -bool find_hw_breakpoint(CPUState *cpu, target_ulong pc); -int insert_hw_breakpoint(target_ulong pc); -int delete_hw_breakpoint(target_ulong pc); +bool find_hw_breakpoint(CPUState *cpu, uint64_t pc); +int insert_hw_breakpoint(uint64_t pc); +int delete_hw_breakpoint(uint64_t pc); bool check_watchpoint_in_range(int i, vaddr addr); CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr); diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c index 0512d67f8cf..4d8fd933868 100644 --- a/target/arm/hyp_gdbstub.c +++ b/target/arm/hyp_gdbstub.c @@ -54,7 +54,7 @@ GArray *hw_breakpoints, *hw_watchpoints; * here so future PC comparisons will work properly. */ -int insert_hw_breakpoint(target_ulong addr) +int insert_hw_breakpoint(uint64_t addr) { HWBreakpoint brk = { .bcr = 0x1, /* BCR E=1, enable */ @@ -80,7 +80,7 @@ int insert_hw_breakpoint(target_ulong addr) * Delete a breakpoint and shuffle any above down */ -int delete_hw_breakpoint(target_ulong pc) +int delete_hw_breakpoint(uint64_t pc) { int i; for (i = 0; i < hw_breakpoints->len; i++) { @@ -226,7 +226,7 @@ int delete_hw_watchpoint(vaddr addr, vaddr len, int type) return -ENOENT; } -bool find_hw_breakpoint(CPUState *cpu, target_ulong pc) +bool find_hw_breakpoint(CPUState *cpu, uint64_t pc) { int i; -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 02/33] include/system/hvf: missing vaddr include 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 01/33] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 03/33] meson: add common libs for target and target_system Pierrick Bouvier ` (30 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier On MacOS x86_64: In file included from ../target/i386/hvf/x86_task.c:13: /Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type name 'vaddr' vaddr pc; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type name 'vaddr' vaddr saved_insn; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:5: error: type name requires a specifier or qualifier QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:18: error: a parameter list without types is only allowed in a function definition QTAILQ_ENTRY(hvf_sw_breakpoint) entry; ^ /Users/runner/work/qemu/qemu/include/system/hvf.h:45:36: error: expected ';' at end of declaration list QTAILQ_ENTRY(hvf_sw_breakpoint) entry; Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- include/system/hvf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/hvf.h b/include/system/hvf.h index 730f927f034..356fced63e3 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -15,6 +15,7 @@ #include "qemu/accel.h" #include "qom/object.h" +#include "exec/vaddr.h" #ifdef COMPILING_PER_TARGET #include "cpu.h" -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 03/33] meson: add common libs for target and target_system 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 01/33] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 02/33] include/system/hvf: missing vaddr include Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 04/33] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier ` (29 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Following what we did for hw/, we need target specific common libraries for target. We need 2 different libraries: - code common to a base architecture - system code common to a base architecture For user code, it can stay compiled per target for now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- meson.build | 78 +++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 17 deletions(-) diff --git a/meson.build b/meson.build index 68d36ac140f..7b2cf3cd7d1 100644 --- a/meson.build +++ b/meson.build @@ -3684,6 +3684,8 @@ target_arch = {} target_system_arch = {} target_user_arch = {} hw_common_arch = {} +target_common_arch = {} +target_common_system_arch = {} # NOTE: the trace/ subdirectory needs the qapi_trace_events variable # that is filled in by qapi/. @@ -4087,29 +4089,59 @@ common_all = static_library('common', # construct common libraries per base architecture hw_common_arch_libs = {} +target_common_arch_libs = {} +target_common_system_arch_libs = {} foreach target : target_dirs config_target = config_target_mak[target] target_base_arch = config_target['TARGET_BASE_ARCH'] + target_inc = [include_directories('target' / target_base_arch)] + inc = [common_user_inc + target_inc] - # check if already generated - if target_base_arch in hw_common_arch_libs - continue - endif + # prevent common code to access cpu compile time definition, + # but still allow access to cpu.h + target_c_args = ['-DCPU_DEFS_H'] + target_system_c_args = target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'] if target_base_arch in hw_common_arch - target_inc = [include_directories('target' / target_base_arch)] - src = hw_common_arch[target_base_arch] - lib = static_library( - 'hw_' + target_base_arch, - build_by_default: false, - sources: src.all_sources() + genh, - include_directories: common_user_inc + target_inc, - implicit_include_directories: false, - # prevent common code to access cpu compile time - # definition, but still allow access to cpu.h - c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU'], - dependencies: src.all_dependencies()) - hw_common_arch_libs += {target_base_arch: lib} + if target_base_arch not in hw_common_arch_libs + src = hw_common_arch[target_base_arch] + lib = static_library( + 'hw_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + hw_common_arch_libs += {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_arch + if target_base_arch not in target_common_arch_libs + src = target_common_arch[target_base_arch] + lib = static_library( + 'target_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_c_args, + dependencies: src.all_dependencies()) + target_common_arch_libs += {target_base_arch: lib} + endif + endif + + if target_base_arch in target_common_system_arch + if target_base_arch not in target_common_system_arch_libs + src = target_common_system_arch[target_base_arch] + lib = static_library( + 'target_system_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: inc, + c_args: target_system_c_args, + dependencies: src.all_dependencies()) + target_common_system_arch_libs += {target_base_arch: lib} + endif endif endforeach @@ -4282,12 +4314,24 @@ foreach target : target_dirs target_common = common_ss.apply(config_target, strict: false) objects = [common_all.extract_objects(target_common.sources())] arch_deps += target_common.dependencies() + if target_base_arch in target_common_arch_libs + src = target_common_arch[target_base_arch].apply(config_target, strict: false) + lib = target_common_arch_libs[target_base_arch] + objects += lib.extract_objects(src.sources()) + arch_deps += src.dependencies() + endif if target_type == 'system' and target_base_arch in hw_common_arch_libs src = hw_common_arch[target_base_arch].apply(config_target, strict: false) lib = hw_common_arch_libs[target_base_arch] objects += lib.extract_objects(src.sources()) arch_deps += src.dependencies() endif + if target_type == 'system' and target_base_arch in target_common_system_arch_libs + src = target_common_system_arch[target_base_arch].apply(config_target, strict: false) + lib = target_common_system_arch_libs[target_base_arch] + objects += lib.extract_objects(src.sources()) + arch_deps += src.dependencies() + endif target_specific = specific_ss.apply(config_target, strict: false) arch_srcs += target_specific.sources() -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 04/33] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (2 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 03/33] meson: add common libs for target and target_system Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 05/33] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier ` (28 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm headers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm_arm.h | 83 +------------------------------------------ target/arm/kvm-stub.c | 77 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 82 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 05c3de8cd46..7b9c7c4a148 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -94,7 +94,7 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); -#ifdef CONFIG_KVM +struct kvm_vcpu_init; /** * kvm_arm_create_scratch_host_vcpu: * @cpus_to_try: array of QEMU_KVM_ARM_TARGET_* values (terminated with @@ -221,85 +221,4 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); void kvm_arm_enable_mte(Object *cpuobj, Error **errp); -#else - -/* - * It's safe to call these functions without KVM support. - * They should either do nothing or return "not supported". - */ -static inline bool kvm_arm_aarch32_supported(void) -{ - return false; -} - -static inline bool kvm_arm_pmu_supported(void) -{ - return false; -} - -static inline bool kvm_arm_sve_supported(void) -{ - return false; -} - -static inline bool kvm_arm_mte_supported(void) -{ - return false; -} - -/* - * These functions should never actually be called without KVM support. - */ -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) -{ - g_assert_not_reached(); -} - -static inline int kvm_arm_vgic_probe(void) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pmu_init(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - g_assert_not_reached(); -} - -static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) -{ - g_assert_not_reached(); -} - -static inline void kvm_arm_enable_mte(Object *cpuobj, Error **errp) -{ - g_assert_not_reached(); -} - -#endif - #endif diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 965a486b320..2b73d0598c1 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -22,3 +22,80 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) { g_assert_not_reached(); } + +/* + * It's safe to call these functions without KVM support. + * They should either do nothing or return "not supported". + */ +bool kvm_arm_aarch32_supported(void) +{ + return false; +} + +bool kvm_arm_pmu_supported(void) +{ + return false; +} + +bool kvm_arm_sve_supported(void) +{ + return false; +} + +bool kvm_arm_mte_supported(void) +{ + return false; +} + +/* + * These functions should never actually be called without KVM support. + */ +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_add_vcpu_properties(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa) +{ + g_assert_not_reached(); +} + +int kvm_arm_vgic_probe(void) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) +{ + g_assert_not_reached(); +} + +void kvm_arm_pmu_init(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) +{ + g_assert_not_reached(); +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) +{ + g_assert_not_reached(); +} + +void kvm_arm_enable_mte(Object *cpuobj, Error **errp) +{ + g_assert_not_reached(); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 05/33] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (3 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 04/33] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier ` (27 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Needed in target/arm/cpu.c once kvm is possible. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm-stub.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 2b73d0598c1..e34d3f5e6b4 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -99,3 +99,8 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) { g_assert_not_reached(); } + +void kvm_arm_reset_vcpu(ARMCPU *cpu) +{ + g_assert_not_reached(); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (4 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 05/33] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 19:04 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 07/33] accel/hvf: add hvf_enabled() for common code Pierrick Bouvier ` (26 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/kvm_arm.h | 2 ++ target/arm/cpu.c | 31 ------------------------------- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 7b9c7c4a148..d156c790b66 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -221,4 +221,6 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); void kvm_arm_enable_mte(Object *cpuobj, Error **errp); +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e951675c60..07f279fec8c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1099,37 +1099,6 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) } } -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu = opaque; - CPUARMState *env = &cpu->env; - CPUState *cs = CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id = KVM_ARM_IRQ_CPU_IRQ; - linestate_bit = CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id = KVM_ARM_IRQ_CPU_FIQ; - linestate_bit = CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |= linestate_bit; - } else { - env->irq_line_state &= ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index e34d3f5e6b4..4806365cdc5 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -104,3 +104,8 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) { g_assert_not_reached(); } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 97de8c7e939..8f68aa10298 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2468,3 +2468,32 @@ void kvm_arm_enable_mte(Object *cpuobj, Error **errp) cpu->kvm_mte = true; } } + +void arm_cpu_kvm_set_irq(void *arm_cpu, int irq, int level) +{ + ARMCPU *cpu = arm_cpu; + CPUARMState *env = &cpu->env; + CPUState *cs = CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id = KVM_ARM_IRQ_CPU_IRQ; + linestate_bit = CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id = KVM_ARM_IRQ_CPU_FIQ; + linestate_bit = CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |= linestate_bit; + } else { + env->irq_line_state &= ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +} -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c 2025-05-01 6:23 ` [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier @ 2025-05-01 19:04 ` Philippe Mathieu-Daudé 2025-05-03 21:12 ` Pierrick Bouvier 0 siblings, 1 reply; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:04 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm (why?) On 1/5/25 08:23, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/kvm_arm.h | 2 ++ > target/arm/cpu.c | 31 ------------------------------- > target/arm/kvm-stub.c | 5 +++++ > target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ > 4 files changed, 36 insertions(+), 31 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c 2025-05-01 19:04 ` Philippe Mathieu-Daudé @ 2025-05-03 21:12 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 21:12 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:04 PM, Philippe Mathieu-Daudé wrote: > (why?) > Allow to get rid of CONFIG_KVM in target/arm/cpu.c. I'll update description with it. > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/kvm_arm.h | 2 ++ >> target/arm/cpu.c | 31 ------------------------------- >> target/arm/kvm-stub.c | 5 +++++ >> target/arm/kvm.c | 29 +++++++++++++++++++++++++++++ >> 4 files changed, 36 insertions(+), 31 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 07/33] accel/hvf: add hvf_enabled() for common code 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (5 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 08/33] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier ` (25 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Other accelerators define a CONFIG_{accel}_IS_POSSIBLE when COMPILING_PER_TARGET is not defined, except hvf. Without this change, target/arm/cpu.c can't find hvf_enabled. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- include/system/hvf.h | 14 +++++++++----- accel/hvf/hvf-stub.c | 5 +++++ accel/hvf/meson.build | 1 + 3 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 accel/hvf/hvf-stub.c diff --git a/include/system/hvf.h b/include/system/hvf.h index 356fced63e3..1ee2a4177d9 100644 --- a/include/system/hvf.h +++ b/include/system/hvf.h @@ -19,15 +19,19 @@ #ifdef COMPILING_PER_TARGET #include "cpu.h" +# ifdef CONFIG_HVF +# define CONFIG_HVF_IS_POSSIBLE +# endif +#else +# define CONFIG_HVF_IS_POSSIBLE +#endif -#ifdef CONFIG_HVF +#ifdef CONFIG_HVF_IS_POSSIBLE extern bool hvf_allowed; #define hvf_enabled() (hvf_allowed) -#else /* !CONFIG_HVF */ +#else #define hvf_enabled() 0 -#endif /* !CONFIG_HVF */ - -#endif /* COMPILING_PER_TARGET */ +#endif /* CONFIG_HVF_IS_POSSIBLE */ #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") diff --git a/accel/hvf/hvf-stub.c b/accel/hvf/hvf-stub.c new file mode 100644 index 00000000000..7f8eaa59099 --- /dev/null +++ b/accel/hvf/hvf-stub.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" + +bool hvf_allowed; diff --git a/accel/hvf/meson.build b/accel/hvf/meson.build index fc52cb78433..7745b94e50f 100644 --- a/accel/hvf/meson.build +++ b/accel/hvf/meson.build @@ -5,3 +5,4 @@ hvf_ss.add(files( )) specific_ss.add_all(when: 'CONFIG_HVF', if_true: hvf_ss) +common_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 08/33] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (6 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 07/33] accel/hvf: add hvf_enabled() for common code Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier ` (24 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07f279fec8c..37b11e8866f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "exec/tswap.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1172,7 +1173,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->endian = BFD_ENDIAN_LITTLE; if (bswap_code(sctlr_b)) { - info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; } info->flags &= ~INSN_ARM_BE32; #ifndef CONFIG_USER_ONLY -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (7 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 08/33] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 19:06 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier ` (23 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37b11e8866f..00ae2778058 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1183,8 +1183,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) #endif } -#ifdef TARGET_AARCH64 - static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu = ARM_CPU(cs); @@ -1342,15 +1340,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -#else - -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - g_assert_not_reached(); -} - -#endif - static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu = ARM_CPU(cs); -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common 2025-05-01 6:23 ` [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier @ 2025-05-01 19:06 ` Philippe Mathieu-Daudé 2025-05-03 21:18 ` Pierrick Bouvier 0 siblings, 1 reply; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:06 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm Missing the "Why?". Answer, because it is guarded by is_a64(). Should we assert on is_a64() on entry? On 1/5/25 08:23, Pierrick Bouvier wrote: > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/cpu.c | 11 ----------- > 1 file changed, 11 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 37b11e8866f..00ae2778058 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1183,8 +1183,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) > #endif > } > > -#ifdef TARGET_AARCH64 > - > static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) > { > ARMCPU *cpu = ARM_CPU(cs); > @@ -1342,15 +1340,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > } > > -#else > - > -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) > -{ > - g_assert_not_reached(); > -} > - > -#endif > - > static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) > { > ARMCPU *cpu = ARM_CPU(cs); ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common 2025-05-01 19:06 ` Philippe Mathieu-Daudé @ 2025-05-03 21:18 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 21:18 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:06 PM, Philippe Mathieu-Daudé wrote: > Missing the "Why?". Answer, because it is guarded by is_a64(). > We are guaranteed it was not used because the whole definition is under TARGET_AARCH64 (and not only the code inside the function). If it was called before, out of this target, it would have triggered a g_assert_not_reached(). As well, yes, it's guarded by is_a64(env). I'll update description with this. > Should we assert on is_a64() on entry? > I don't think so, from the reason above 'If it was called before'. > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/cpu.c | 11 ----------- >> 1 file changed, 11 deletions(-) >> >> diff --git a/target/arm/cpu.c b/target/arm/cpu.c >> index 37b11e8866f..00ae2778058 100644 >> --- a/target/arm/cpu.c >> +++ b/target/arm/cpu.c >> @@ -1183,8 +1183,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) >> #endif >> } >> >> -#ifdef TARGET_AARCH64 >> - >> static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> { >> ARMCPU *cpu = ARM_CPU(cs); >> @@ -1342,15 +1340,6 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> } >> } >> >> -#else >> - >> -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> -{ >> - g_assert_not_reached(); >> -} >> - >> -#endif >> - >> static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) >> { >> ARMCPU *cpu = ARM_CPU(cs); > ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (8 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 19:06 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 11/33] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier ` (22 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Need to stub cpu64 finalize functions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/cpu.c | 2 -- target/arm/cpu32-stubs.c | 26 ++++++++++++++++++++++++++ target/arm/meson.build | 11 +++++++---- 3 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 target/arm/cpu32-stubs.c diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 00ae2778058..c3a1e8e284d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1878,7 +1878,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) { Error *local_err = NULL; -#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err != NULL) { @@ -1914,7 +1913,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } } -#endif if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c new file mode 100644 index 00000000000..81be44d8462 --- /dev/null +++ b/target/arm/cpu32-stubs.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "target/arm/cpu.h" +#include "target/arm/internals.h" +#include <glib.h> + +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} + +void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +{ + g_assert_not_reached(); +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241..c39ddc4427b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,10 +11,13 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', -)) +arm_ss.add(when: 'TARGET_AARCH64', + if_true: files( + 'cpu64.c', + 'gdbstub64.c'), + if_false: files( + 'cpu32-stubs.c'), +) arm_system_ss = ss.source_set() arm_system_ss.add(files( -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features 2025-05-01 6:23 ` [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier @ 2025-05-01 19:06 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:06 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Need to stub cpu64 finalize functions. > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/cpu.c | 2 -- > target/arm/cpu32-stubs.c | 26 ++++++++++++++++++++++++++ > target/arm/meson.build | 11 +++++++---- > 3 files changed, 33 insertions(+), 6 deletions(-) > create mode 100644 target/arm/cpu32-stubs.c Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 11/33] target/arm/cpu: compile file twice (user, system) only 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (9 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 12/33] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier ` (21 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c39ddc4427b..89e305eb56a 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,6 @@ arm_ss = ss.source_set() +arm_common_ss = ss.source_set() arm_ss.add(files( - 'cpu.c', 'debug_helper.c', 'gdbstub.c', 'helper.c', @@ -20,6 +20,7 @@ arm_ss.add(when: 'TARGET_AARCH64', ) arm_system_ss = ss.source_set() +arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', @@ -30,6 +31,9 @@ arm_system_ss.add(files( )) arm_user_ss = ss.source_set() +arm_user_ss.add(files('cpu.c')) + +arm_common_system_ss.add(files('cpu.c'), capstone) subdir('hvf') @@ -42,3 +46,5 @@ endif target_arch += {'arm': arm_ss} target_system_arch += {'arm': arm_system_ss} target_user_arch += {'arm': arm_user_ss} +target_common_arch += {'arm': arm_common_ss} +target_common_system_arch += {'arm': arm_common_system_ss} -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 12/33] target/arm/cpu32-stubs.c: compile file twice (user, system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (10 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 11/33] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment Pierrick Bouvier ` (20 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier It could be squashed with commit introducing it, but I would prefer to introduce target/arm/cpu.c first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 89e305eb56a..de214fe5d56 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,13 +11,9 @@ arm_ss.add(zlib) arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -arm_ss.add(when: 'TARGET_AARCH64', - if_true: files( - 'cpu64.c', - 'gdbstub64.c'), - if_false: files( - 'cpu32-stubs.c'), -) +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c')) arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() @@ -32,8 +28,12 @@ arm_system_ss.add(files( arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) +arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) arm_common_system_ss.add(files('cpu.c'), capstone) +arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( + 'cpu32-stubs.c')) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (11 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 12/33] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:02 ` Richard Henderson 2025-05-01 16:30 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 14/33] target/arm/helper: user i64 for probe_access Pierrick Bouvier ` (19 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 09075058391..450c9d841bf 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8841f039bc6..943b8438fc7 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; int target_el = exception_target_el(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 43408c71bbd..2fe8ada803a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10247,7 +10247,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_i64(pc)); s->base.is_jmp = DISAS_NORETURN; s->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 273b860d572..1577ef697b2 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7801,7 +7801,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns == 1); - gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_i64(pc)); dc->base.is_jmp = DISAS_NORETURN; dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); return; -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment 2025-05-01 6:23 ` [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment Pierrick Bouvier @ 2025-05-01 15:02 ` Richard Henderson 2025-05-01 16:30 ` Richard Henderson 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:02 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 2 +- > target/arm/tcg/tlb_helper.c | 2 +- > target/arm/tcg/translate-a64.c | 2 +- > target/arm/tcg/translate.c | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment 2025-05-01 6:23 ` [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment Pierrick Bouvier 2025-05-01 15:02 ` Richard Henderson @ 2025-05-01 16:30 ` Richard Henderson 2025-05-03 21:54 ` Pierrick Bouvier 1 sibling, 1 reply; 79+ messages in thread From: Richard Henderson @ 2025-05-01 16:30 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > --- a/target/arm/helper.h > +++ b/target/arm/helper.h > @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) > DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) > DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) > DEF_HELPER_2(exception_swstep, noreturn, env, i32) > -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) > +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) > DEF_HELPER_1(setend, void, env) > DEF_HELPER_2(wfi, void, env, i32) > DEF_HELPER_1(wfe, void, env) > diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c > index 8841f039bc6..943b8438fc7 100644 > --- a/target/arm/tcg/tlb_helper.c > +++ b/target/arm/tcg/tlb_helper.c > @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); > } > > -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) > +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) > { > ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; > int target_el = exception_target_el(env); I think for this and the next patch, it would be worth extending include/exec/helper-head.h.inc and include/tcg/ to allow vaddr. r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment 2025-05-01 16:30 ` Richard Henderson @ 2025-05-03 21:54 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 21:54 UTC (permalink / raw) To: Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/1/25 9:30 AM, Richard Henderson wrote: > On 4/30/25 23:23, Pierrick Bouvier wrote: >> --- a/target/arm/helper.h >> +++ b/target/arm/helper.h >> @@ -49,7 +49,7 @@ DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) >> DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) >> DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) >> DEF_HELPER_2(exception_swstep, noreturn, env, i32) >> -DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) >> +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) >> DEF_HELPER_1(setend, void, env) >> DEF_HELPER_2(wfi, void, env, i32) >> DEF_HELPER_1(wfe, void, env) >> diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c >> index 8841f039bc6..943b8438fc7 100644 >> --- a/target/arm/tcg/tlb_helper.c >> +++ b/target/arm/tcg/tlb_helper.c >> @@ -277,7 +277,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, >> arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); >> } >> >> -void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) >> +void helper_exception_pc_alignment(CPUARMState *env, uint64_t pc) >> { >> ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; >> int target_el = exception_target_el(env); > > I think for this and the next patch, it would be worth extending > include/exec/helper-head.h.inc and include/tcg/ to allow vaddr. > Ok, I'll add it. > > r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 14/33] target/arm/helper: user i64 for probe_access 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (12 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 15/33] target/arm/helper: extract common helpers Pierrick Bouvier ` (18 subsequent siblings) 32 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 2 +- target/arm/tcg/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 450c9d841bf..f870b707c7f 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -104,7 +104,7 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, i64, i32, i32, i32) DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 38d49cbb9d8..32344bd06d1 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -1222,7 +1222,7 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) } } -void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, +void HELPER(probe_access)(CPUARMState *env, uint64_t ptr, uint32_t access_type, uint32_t mmu_idx, uint32_t size) { -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* [PATCH v3 15/33] target/arm/helper: extract common helpers 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (13 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 14/33] target/arm/helper: user i64 for probe_access Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:06 ` Richard Henderson 2025-05-01 15:07 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 16/33] target/arm/debug_helper: only include " Pierrick Bouvier ` (17 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.h | 1152 +------------------------------------- target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 1155 insertions(+), 1150 deletions(-) create mode 100644 target/arm/tcg/helper.h diff --git a/target/arm/helper.h b/target/arm/helper.h index f870b707c7f..f340a49a28a 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,1154 +1,6 @@ -DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) -DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) +/* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF_HELPER_3(add_setq, i32, env, i32, i32) -DEF_HELPER_3(add_saturate, i32, env, i32, i32) -DEF_HELPER_3(sub_saturate, i32, env, i32, i32) -DEF_HELPER_3(add_usaturate, i32, env, i32, i32) -DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) -DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) - -#define PAS_OP(pfx) \ - DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ - DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) - -PAS_OP(s) -PAS_OP(u) -#undef PAS_OP - -#define PAS_OP(pfx) \ - DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ - DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ - DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ - DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) -PAS_OP(q) -PAS_OP(sh) -PAS_OP(uq) -PAS_OP(uh) -#undef PAS_OP - -DEF_HELPER_3(ssat, i32, env, i32, i32) -DEF_HELPER_3(usat, i32, env, i32, i32) -DEF_HELPER_3(ssat16, i32, env, i32, i32) -DEF_HELPER_3(usat16, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) - -DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, - i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, noreturn, env, i32) -DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) -DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) -DEF_HELPER_2(exception_swstep, noreturn, env, i32) -DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) -DEF_HELPER_1(setend, void, env) -DEF_HELPER_2(wfi, void, env, i32) -DEF_HELPER_1(wfe, void, env) -DEF_HELPER_2(wfit, void, env, i64) -DEF_HELPER_1(yield, void, env) -DEF_HELPER_1(pre_hvc, void, env) -DEF_HELPER_2(pre_smc, void, env, i32) -DEF_HELPER_1(vesb, void, env) - -DEF_HELPER_3(cpsr_write, void, env, i32, i32) -DEF_HELPER_2(cpsr_write_eret, void, env, i32) -DEF_HELPER_1(cpsr_read, i32, env) - -DEF_HELPER_3(v7m_msr, void, env, i32, i32) -DEF_HELPER_2(v7m_mrs, i32, env, i32) - -DEF_HELPER_2(v7m_bxns, void, env, i32) -DEF_HELPER_2(v7m_blxns, void, env, i32) - -DEF_HELPER_3(v7m_tt, i32, env, i32, i32) - -DEF_HELPER_1(v7m_preserve_fp_state, void, env) - -DEF_HELPER_2(v7m_vlstm, void, env, i32) -DEF_HELPER_2(v7m_vlldm, void, env, i32) - -DEF_HELPER_2(v8m_stackcheck, void, env, i32) - -DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) - -DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) -DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) -DEF_HELPER_2(get_cp_reg, i32, env, cptr) -DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) -DEF_HELPER_2(get_cp_reg64, i64, env, cptr) - -DEF_HELPER_2(get_r13_banked, i32, env, i32) -DEF_HELPER_3(set_r13_banked, void, env, i32, i32) - -DEF_HELPER_3(mrs_banked, i32, env, i32, i32) -DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) - -DEF_HELPER_2(get_user_reg, i32, env, i32) -DEF_HELPER_3(set_user_reg, void, env, i32, i32) - -DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) - -DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, i64, i32, i32, i32) - -DEF_HELPER_1(vfp_get_fpscr, i32, env) -DEF_HELPER_2(vfp_set_fpscr, void, env, i32) - -DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst) -DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst) -DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst) -DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst) -DEF_HELPER_2(vfp_sqrth, f16, f16, fpst) -DEF_HELPER_2(vfp_sqrts, f32, f32, fpst) -DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst) -DEF_HELPER_3(vfp_cmph, void, f16, f16, env) -DEF_HELPER_3(vfp_cmps, void, f32, f32, env) -DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) -DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) -DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) -DEF_HELPER_3(vfp_cmped, void, f64, f64, env) - -DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst) -DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst) -DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst) -DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst) - -DEF_HELPER_2(vfp_uitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_uitos, f32, i32, fpst) -DEF_HELPER_2(vfp_uitod, f64, i32, fpst) -DEF_HELPER_2(vfp_sitoh, f16, i32, fpst) -DEF_HELPER_2(vfp_sitos, f32, i32, fpst) -DEF_HELPER_2(vfp_sitod, f64, i32, fpst) - -DEF_HELPER_2(vfp_touih, i32, f16, fpst) -DEF_HELPER_2(vfp_touis, i32, f32, fpst) -DEF_HELPER_2(vfp_touid, i32, f64, fpst) -DEF_HELPER_2(vfp_touizh, i32, f16, fpst) -DEF_HELPER_2(vfp_touizs, i32, f32, fpst) -DEF_HELPER_2(vfp_touizd, i32, f64, fpst) -DEF_HELPER_2(vfp_tosih, s32, f16, fpst) -DEF_HELPER_2(vfp_tosis, s32, f32, fpst) -DEF_HELPER_2(vfp_tosid, s32, f64, fpst) -DEF_HELPER_2(vfp_tosizh, s32, f16, fpst) -DEF_HELPER_2(vfp_tosizs, s32, f32, fpst) -DEF_HELPER_2(vfp_tosizd, s32, f64, fpst) - -DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst) -DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst) -DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst) -DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst) -DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst) -DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst) -DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst) -DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst) - -DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst) -DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst) -DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst) -DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst) - -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst) - -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32) - -DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst) -DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst) -DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst) - -DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) - -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) -DEF_HELPER_3(ror_cc, i32, env, i32, i32) - -DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst) -DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) -DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst) - -DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) - -/* neon_helper.c */ -DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) - -DEF_HELPER_2(neon_shl_u16, i32, i32, i32) -DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) -DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) -DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_srshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_urshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_urshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_2(neon_add_u8, i32, i32, i32) -DEF_HELPER_2(neon_add_u16, i32, i32, i32) -DEF_HELPER_2(neon_sub_u8, i32, i32, i32) -DEF_HELPER_2(neon_sub_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_u8, i32, i32, i32) -DEF_HELPER_2(neon_mul_u16, i32, i32, i32) - -DEF_HELPER_2(neon_tst_u8, i32, i32, i32) -DEF_HELPER_2(neon_tst_u16, i32, i32, i32) -DEF_HELPER_2(neon_tst_u32, i32, i32, i32) - -DEF_HELPER_1(neon_clz_u8, i32, i32) -DEF_HELPER_1(neon_clz_u16, i32, i32) -DEF_HELPER_1(neon_cls_s8, i32, i32) -DEF_HELPER_1(neon_cls_s16, i32, i32) -DEF_HELPER_1(neon_cls_s32, i32, i32) -DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) -DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) -DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) -DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) - -DEF_HELPER_1(neon_narrow_u8, i64, i64) -DEF_HELPER_1(neon_narrow_u16, i64, i64) -DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) -DEF_HELPER_1(neon_narrow_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_high_u16, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) -DEF_HELPER_1(neon_widen_u8, i64, i32) -DEF_HELPER_1(neon_widen_s8, i64, i32) -DEF_HELPER_1(neon_widen_u16, i64, i32) -DEF_HELPER_1(neon_widen_s16, i64, i32) - -DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) -DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) -DEF_HELPER_2(neon_mull_u8, i64, i32, i32) -DEF_HELPER_2(neon_mull_s8, i64, i32, i32) -DEF_HELPER_2(neon_mull_u16, i64, i32, i32) -DEF_HELPER_2(neon_mull_s16, i64, i32, i32) - -DEF_HELPER_1(neon_negl_u16, i64, i64) -DEF_HELPER_1(neon_negl_u32, i64, i64) - -DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) - -DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) -DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) -DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) - -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - -DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) - -DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) - -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_sdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ah_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ah_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ah_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst) -DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst) -DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst) - -DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ssra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_usra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_usra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_urshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_srsra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_srsra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_ursra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_sli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_sli_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, env, i32) - -DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) -DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) - -DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_addp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_smaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_smaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_sminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_sminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_umaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_umaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +#include "tcg/helper.h" #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h" diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h new file mode 100644 index 00000000000..da34b22e180 --- /dev/null +++ b/target/arm/tcg/helper.h @@ -0,0 +1,1153 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32) +DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32) + +DEF_HELPER_3(add_setq, i32, env, i32, i32) +DEF_HELPER_3(add_saturate, i32, env, i32, i32) +DEF_HELPER_3(sub_saturate, i32, env, i32, i32) +DEF_HELPER_3(add_usaturate, i32, env, i32, i32) +DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) + +#define PAS_OP(pfx) \ + DEF_HELPER_3(pfx ## add8, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## sub8, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## sub16, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## add16, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## addsubx, i32, i32, i32, ptr) \ + DEF_HELPER_3(pfx ## subaddx, i32, i32, i32, ptr) + +PAS_OP(s) +PAS_OP(u) +#undef PAS_OP + +#define PAS_OP(pfx) \ + DEF_HELPER_2(pfx ## add8, i32, i32, i32) \ + DEF_HELPER_2(pfx ## sub8, i32, i32, i32) \ + DEF_HELPER_2(pfx ## sub16, i32, i32, i32) \ + DEF_HELPER_2(pfx ## add16, i32, i32, i32) \ + DEF_HELPER_2(pfx ## addsubx, i32, i32, i32) \ + DEF_HELPER_2(pfx ## subaddx, i32, i32, i32) +PAS_OP(q) +PAS_OP(sh) +PAS_OP(uq) +PAS_OP(uh) +#undef PAS_OP + +DEF_HELPER_3(ssat, i32, env, i32, i32) +DEF_HELPER_3(usat, i32, env, i32, i32) +DEF_HELPER_3(ssat16, i32, env, i32, i32) +DEF_HELPER_3(usat16, i32, env, i32, i32) + +DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) + +DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, + i32, i32, i32, i32) +DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) +DEF_HELPER_2(exception_swstep, noreturn, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, i64) +DEF_HELPER_1(setend, void, env) +DEF_HELPER_2(wfi, void, env, i32) +DEF_HELPER_1(wfe, void, env) +DEF_HELPER_2(wfit, void, env, i64) +DEF_HELPER_1(yield, void, env) +DEF_HELPER_1(pre_hvc, void, env) +DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) + +DEF_HELPER_3(cpsr_write, void, env, i32, i32) +DEF_HELPER_2(cpsr_write_eret, void, env, i32) +DEF_HELPER_1(cpsr_read, i32, env) + +DEF_HELPER_3(v7m_msr, void, env, i32, i32) +DEF_HELPER_2(v7m_mrs, i32, env, i32) + +DEF_HELPER_2(v7m_bxns, void, env, i32) +DEF_HELPER_2(v7m_blxns, void, env, i32) + +DEF_HELPER_3(v7m_tt, i32, env, i32, i32) + +DEF_HELPER_1(v7m_preserve_fp_state, void, env) + +DEF_HELPER_2(v7m_vlstm, void, env, i32) +DEF_HELPER_2(v7m_vlldm, void, env, i32) + +DEF_HELPER_2(v8m_stackcheck, void, env, i32) + +DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) + +DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) +DEF_HELPER_FLAGS_2(lookup_cp_reg, TCG_CALL_NO_RWG_SE, cptr, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el0, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(tidcp_el1, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_3(set_cp_reg, void, env, cptr, i32) +DEF_HELPER_2(get_cp_reg, i32, env, cptr) +DEF_HELPER_3(set_cp_reg64, void, env, cptr, i64) +DEF_HELPER_2(get_cp_reg64, i64, env, cptr) + +DEF_HELPER_2(get_r13_banked, i32, env, i32) +DEF_HELPER_3(set_r13_banked, void, env, i32, i32) + +DEF_HELPER_3(mrs_banked, i32, env, i32, i32) +DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) + +DEF_HELPER_2(get_user_reg, i32, env, i32) +DEF_HELPER_3(set_user_reg, void, env, i32, i32) + +DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + +DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, i64, i32, i32, i32) + +DEF_HELPER_1(vfp_get_fpscr, i32, env) +DEF_HELPER_2(vfp_set_fpscr, void, env, i32) + +DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst) +DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst) +DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst) +DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst) +DEF_HELPER_2(vfp_sqrth, f16, f16, fpst) +DEF_HELPER_2(vfp_sqrts, f32, f32, fpst) +DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst) +DEF_HELPER_3(vfp_cmph, void, f16, f16, env) +DEF_HELPER_3(vfp_cmps, void, f32, f32, env) +DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) +DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) +DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) +DEF_HELPER_3(vfp_cmped, void, f64, f64, env) + +DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst) +DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst) +DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst) +DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst) + +DEF_HELPER_2(vfp_uitoh, f16, i32, fpst) +DEF_HELPER_2(vfp_uitos, f32, i32, fpst) +DEF_HELPER_2(vfp_uitod, f64, i32, fpst) +DEF_HELPER_2(vfp_sitoh, f16, i32, fpst) +DEF_HELPER_2(vfp_sitos, f32, i32, fpst) +DEF_HELPER_2(vfp_sitod, f64, i32, fpst) + +DEF_HELPER_2(vfp_touih, i32, f16, fpst) +DEF_HELPER_2(vfp_touis, i32, f32, fpst) +DEF_HELPER_2(vfp_touid, i32, f64, fpst) +DEF_HELPER_2(vfp_touizh, i32, f16, fpst) +DEF_HELPER_2(vfp_touizs, i32, f32, fpst) +DEF_HELPER_2(vfp_touizd, i32, f64, fpst) +DEF_HELPER_2(vfp_tosih, s32, f16, fpst) +DEF_HELPER_2(vfp_tosis, s32, f32, fpst) +DEF_HELPER_2(vfp_tosid, s32, f64, fpst) +DEF_HELPER_2(vfp_tosizh, s32, f16, fpst) +DEF_HELPER_2(vfp_tosizs, s32, f32, fpst) +DEF_HELPER_2(vfp_tosizd, s32, f64, fpst) + +DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst) +DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst) +DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst) +DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst) +DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst) +DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst) +DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst) + +DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst) +DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst) +DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst) +DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst) + +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst) + +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32) + +DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst) +DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst) +DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst) + +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) + +DEF_HELPER_3(shl_cc, i32, env, i32, i32) +DEF_HELPER_3(shr_cc, i32, env, i32, i32) +DEF_HELPER_3(sar_cc, i32, env, i32, i32) +DEF_HELPER_3(ror_cc, i32, env, i32, i32) + +DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst) +DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst) + +DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst) + +DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) + +/* neon_helper.c */ +DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) + +DEF_HELPER_2(neon_shl_u16, i32, i32, i32) +DEF_HELPER_2(neon_shl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) +DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) +DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) +DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_srshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_urshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_urshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_2(neon_add_u8, i32, i32, i32) +DEF_HELPER_2(neon_add_u16, i32, i32, i32) +DEF_HELPER_2(neon_sub_u8, i32, i32, i32) +DEF_HELPER_2(neon_sub_u16, i32, i32, i32) +DEF_HELPER_2(neon_mul_u8, i32, i32, i32) +DEF_HELPER_2(neon_mul_u16, i32, i32, i32) + +DEF_HELPER_2(neon_tst_u8, i32, i32, i32) +DEF_HELPER_2(neon_tst_u16, i32, i32, i32) +DEF_HELPER_2(neon_tst_u32, i32, i32, i32) + +DEF_HELPER_1(neon_clz_u8, i32, i32) +DEF_HELPER_1(neon_clz_u16, i32, i32) +DEF_HELPER_1(neon_cls_s8, i32, i32) +DEF_HELPER_1(neon_cls_s16, i32, i32) +DEF_HELPER_1(neon_cls_s32, i32, i32) +DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) +DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) + +DEF_HELPER_1(neon_narrow_u8, i64, i64) +DEF_HELPER_1(neon_narrow_u16, i64, i64) +DEF_HELPER_2(neon_unarrow_sat8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u8, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s8, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u16, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s16, i64, env, i64) +DEF_HELPER_2(neon_unarrow_sat32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_u32, i64, env, i64) +DEF_HELPER_2(neon_narrow_sat_s32, i64, env, i64) +DEF_HELPER_1(neon_narrow_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_high_u16, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) +DEF_HELPER_1(neon_widen_u8, i64, i32) +DEF_HELPER_1(neon_widen_s8, i64, i32) +DEF_HELPER_1(neon_widen_u16, i64, i32) +DEF_HELPER_1(neon_widen_s16, i64, i32) + +DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) +DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) +DEF_HELPER_2(neon_mull_u8, i64, i32, i32) +DEF_HELPER_2(neon_mull_s8, i64, i32, i32) +DEF_HELPER_2(neon_mull_u16, i64, i32, i32) +DEF_HELPER_2(neon_mull_s16, i64, i32, i32) + +DEF_HELPER_1(neon_negl_u16, i64, i64) +DEF_HELPER_1(neon_negl_u32, i64, i64) + +DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) + +DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst) +DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst) +DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst) + +/* iwmmxt_helper.c */ +DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) +DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) + +#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ +DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ + +DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) +DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) + +DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) + +DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) + +DEF_IWMMXT_HELPER_SIZE_ENV(mins) +DEF_IWMMXT_HELPER_SIZE_ENV(minu) +DEF_IWMMXT_HELPER_SIZE_ENV(maxs) +DEF_IWMMXT_HELPER_SIZE_ENV(maxu) + +DEF_IWMMXT_HELPER_SIZE_ENV(subn) +DEF_IWMMXT_HELPER_SIZE_ENV(addn) +DEF_IWMMXT_HELPER_SIZE_ENV(subu) +DEF_IWMMXT_HELPER_SIZE_ENV(addu) +DEF_IWMMXT_HELPER_SIZE_ENV(subs) +DEF_IWMMXT_HELPER_SIZE_ENV(adds) + +DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) +DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) + +DEF_HELPER_1(iwmmxt_bcstb, i64, i32) +DEF_HELPER_1(iwmmxt_bcstw, i64, i32) +DEF_HELPER_1(iwmmxt_bcstl, i64, i32) + +DEF_HELPER_1(iwmmxt_addcb, i64, i64) +DEF_HELPER_1(iwmmxt_addcw, i64, i64) +DEF_HELPER_1(iwmmxt_addcl, i64, i64) + +DEF_HELPER_1(iwmmxt_msbb, i32, i64) +DEF_HELPER_1(iwmmxt_msbw, i32, i64) +DEF_HELPER_1(iwmmxt_msbl, i32, i64) + +DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) + +DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) + +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) +DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) + +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_sdot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ah_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ah_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ah_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_fmls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_fmls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_ah_fmls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst) +DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst) +DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst) + +DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_smulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ssra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_usra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_usra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_srshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_urshr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_urshr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_srsra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_srsra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_ursra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursra_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_sri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_sli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_sli_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uabd_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_saba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_saba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uaba_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmlah_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmlsh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_ummla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_usmmla_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(gvec_bfdot, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_FLAGS_6(gvec_bfdot_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) +DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) + +DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_addp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_smaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_smaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_umaxp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_umaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 15/33] target/arm/helper: extract common helpers 2025-05-01 6:23 ` [PATCH v3 15/33] target/arm/helper: extract common helpers Pierrick Bouvier @ 2025-05-01 15:06 ` Richard Henderson 2025-05-01 15:24 ` Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 1 sibling, 1 reply; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:06 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 1152 +------------------------------------- > target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 1155 insertions(+), 1150 deletions(-) > create mode 100644 target/arm/tcg/helper.h Why? r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 15/33] target/arm/helper: extract common helpers 2025-05-01 15:06 ` Richard Henderson @ 2025-05-01 15:24 ` Pierrick Bouvier 2025-05-03 22:11 ` Pierrick Bouvier 0 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 15:24 UTC (permalink / raw) To: Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/1/25 8:06 AM, Richard Henderson wrote: > On 4/30/25 23:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> >> --- >> target/arm/helper.h | 1152 +------------------------------------- >> target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 1155 insertions(+), 1150 deletions(-) >> create mode 100644 target/arm/tcg/helper.h > > Why? > It allows later commits to include only the "new" tcg/helper.h, and thus preventing to pull aarch64 helpers (+ target/arm/helper.h contains a ifdef TARGET_AARCH64). As well, for work on target/arm/tcg/, we'll need to have aarch64 helpers splitted from common ones. Makes more sense? > r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 15/33] target/arm/helper: extract common helpers 2025-05-01 15:24 ` Pierrick Bouvier @ 2025-05-03 22:11 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:11 UTC (permalink / raw) To: Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/1/25 8:24 AM, Pierrick Bouvier wrote: > On 5/1/25 8:06 AM, Richard Henderson wrote: >> On 4/30/25 23:23, Pierrick Bouvier wrote: >>> Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> >>> --- >>> target/arm/helper.h | 1152 +------------------------------------- >>> target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ >>> 2 files changed, 1155 insertions(+), 1150 deletions(-) >>> create mode 100644 target/arm/tcg/helper.h >> >> Why? >> > > It allows later commits to include only the "new" tcg/helper.h, and thus > preventing to pull aarch64 helpers (+ target/arm/helper.h contains a > ifdef TARGET_AARCH64). > > As well, for work on target/arm/tcg/, we'll need to have aarch64 helpers > splitted from common ones. > > Makes more sense? > Added a better description to commit message. >> r~ > ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 15/33] target/arm/helper: extract common helpers 2025-05-01 6:23 ` [PATCH v3 15/33] target/arm/helper: extract common helpers Pierrick Bouvier 2025-05-01 15:06 ` Richard Henderson @ 2025-05-01 15:07 ` Richard Henderson 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.h | 1152 +------------------------------------- > target/arm/tcg/helper.h | 1153 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 1155 insertions(+), 1150 deletions(-) > create mode 100644 target/arm/tcg/helper.h Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 16/33] target/arm/debug_helper: only include common helpers 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (14 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 15/33] target/arm/helper: extract common helpers Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong Pierrick Bouvier ` (16 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Avoid pulling helper.h which contains TARGET_AARCH64. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/debug_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 473ee2af38e..357bc2141ae 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,10 +12,12 @@ #include "cpu-features.h" #include "cpregs.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/tcg.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 16/33] target/arm/debug_helper: only include common helpers 2025-05-01 6:23 ` [PATCH v3 16/33] target/arm/debug_helper: only include " Pierrick Bouvier @ 2025-05-01 15:07 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Avoid pulling helper.h which contains TARGET_AARCH64. > > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/debug_helper.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c > index 473ee2af38e..357bc2141ae 100644 > --- a/target/arm/debug_helper.c > +++ b/target/arm/debug_helper.c > @@ -12,10 +12,12 @@ > #include "cpu-features.h" > #include "cpregs.h" > #include "exec/exec-all.h" > -#include "exec/helper-proto.h" > #include "exec/watchpoint.h" > #include "system/tcg.h" > > +#define HELPER_H "tcg/helper.h" > +#include "exec/helper-proto.h.inc" > + > #ifdef CONFIG_TCG > /* Return the Exception Level targeted by debug exceptions. */ > static int arm_debug_target_el(CPUARMState *env) Oh, I see. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (15 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 16/33] target/arm/debug_helper: only include " Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 2025-05-01 19:26 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier ` (15 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 357bc2141ae..50ef5618f51 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -381,7 +381,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong pc; + vaddr pc; int n; /* -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong 2025-05-01 6:23 ` [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong Pierrick Bouvier @ 2025-05-01 15:07 ` Richard Henderson 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-01 19:26 ` Philippe Mathieu-Daudé 1 sibling, 1 reply; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:07 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/debug_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c > index 357bc2141ae..50ef5618f51 100644 > --- a/target/arm/debug_helper.c > +++ b/target/arm/debug_helper.c > @@ -381,7 +381,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) > { > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > - target_ulong pc; > + vaddr pc; > int n; > > /* Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong 2025-05-01 15:07 ` Richard Henderson @ 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-03 22:16 ` Pierrick Bouvier 0 siblings, 1 reply; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:28 UTC (permalink / raw) To: Richard Henderson, Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 17:07, Richard Henderson wrote: > On 4/30/25 23:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/debug_helper.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c >> index 357bc2141ae..50ef5618f51 100644 >> --- a/target/arm/debug_helper.c >> +++ b/target/arm/debug_helper.c >> @@ -381,7 +381,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) >> { >> ARMCPU *cpu = ARM_CPU(cs); >> CPUARMState *env = &cpu->env; >> - target_ulong pc; >> + vaddr pc; Why not directly use the symbol type (uint64_t)? >> int n; >> /* > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong 2025-05-01 19:28 ` Philippe Mathieu-Daudé @ 2025-05-03 22:16 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:16 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:28 PM, Philippe Mathieu-Daudé wrote: > On 1/5/25 17:07, Richard Henderson wrote: >> On 4/30/25 23:23, Pierrick Bouvier wrote: >>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >>> --- >>> target/arm/debug_helper.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c >>> index 357bc2141ae..50ef5618f51 100644 >>> --- a/target/arm/debug_helper.c >>> +++ b/target/arm/debug_helper.c >>> @@ -381,7 +381,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) >>> { >>> ARMCPU *cpu = ARM_CPU(cs); >>> CPUARMState *env = &cpu->env; >>> - target_ulong pc; >>> + vaddr pc; > > Why not directly use the symbol type (uint64_t)? > IIRC, Richard mentioned "use vaddr instead of uint64_t for pc" on another series. >>> int n; >>> /* >> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> >> r~ > ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong 2025-05-01 6:23 ` [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson @ 2025-05-01 19:26 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:26 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/debug_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (16 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:14 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 19/33] target/arm/helper: restrict include to common helpers Pierrick Bouvier ` (14 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index de214fe5d56..48a6bf59353 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,7 +1,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( - 'debug_helper.c', 'gdbstub.c', 'helper.c', 'vfp_fpscr.c', @@ -29,11 +28,18 @@ arm_system_ss.add(files( arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( - 'cpu32-stubs.c')) + 'cpu32-stubs.c', +)) +arm_user_ss.add(files( + 'debug_helper.c', +)) arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(files( + 'debug_helper.c', +)) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) 2025-05-01 6:23 ` [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-01 15:14 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:14 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 19/33] target/arm/helper: restrict include to common helpers 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (17 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:15 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier ` (13 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 257b1ba5270..085c1656027 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "exec/helper-proto.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "qemu/main-loop.h" @@ -36,6 +35,9 @@ #include "target/arm/gtimer.h" #include "qemu/plugin.h" +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ static void switch_mode(CPUARMState *env, int mode); -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 19/33] target/arm/helper: restrict include to common helpers 2025-05-01 6:23 ` [PATCH v3 19/33] target/arm/helper: restrict include to common helpers Pierrick Bouvier @ 2025-05-01 15:15 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:15 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 257b1ba5270..085c1656027 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -12,7 +12,6 @@ > #include "cpu.h" > #include "internals.h" > #include "cpu-features.h" > -#include "exec/helper-proto.h" > #include "exec/page-protection.h" > #include "exec/mmap-lock.h" > #include "qemu/main-loop.h" > @@ -36,6 +35,9 @@ > #include "target/arm/gtimer.h" > #include "qemu/plugin.h" > > +#define HELPER_H "tcg/helper.h" > +#include "exec/helper-proto.h.inc" > + > #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ > > static void switch_mode(CPUARMState *env, int mode); Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (18 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 19/33] target/arm/helper: restrict include to common helpers Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:15 ` Richard Henderson 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier ` (12 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 085c1656027..595d9334977 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10641,7 +10641,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; unsigned int new_el = env->exception.target_el; - target_ulong addr = env->cp15.vbar_el[new_el]; + vaddr addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int old_mode; unsigned int cur_el = arm_current_el(env); -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr 2025-05-01 6:23 ` [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier @ 2025-05-01 15:15 ` Richard Henderson 2025-05-01 19:28 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:15 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 085c1656027..595d9334977 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -10641,7 +10641,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > unsigned int new_el = env->exception.target_el; > - target_ulong addr = env->cp15.vbar_el[new_el]; > + vaddr addr = env->cp15.vbar_el[new_el]; > unsigned int new_mode = aarch64_pstate_mode(new_el, true); > unsigned int old_mode; > unsigned int cur_el = arm_current_el(env); Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr 2025-05-01 6:23 ` [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier 2025-05-01 15:15 ` Richard Henderson @ 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-03 22:20 ` Pierrick Bouvier 1 sibling, 1 reply; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:28 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 085c1656027..595d9334977 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -10641,7 +10641,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) > ARMCPU *cpu = ARM_CPU(cs); > CPUARMState *env = &cpu->env; > unsigned int new_el = env->exception.target_el; > - target_ulong addr = env->cp15.vbar_el[new_el]; > + vaddr addr = env->cp15.vbar_el[new_el]; Why not directly use the symbol type (uint64_t)? Anyway, Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr 2025-05-01 19:28 ` Philippe Mathieu-Daudé @ 2025-05-03 22:20 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:20 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:28 PM, Philippe Mathieu-Daudé wrote: > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/helper.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/helper.c b/target/arm/helper.c >> index 085c1656027..595d9334977 100644 >> --- a/target/arm/helper.c >> +++ b/target/arm/helper.c >> @@ -10641,7 +10641,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) >> ARMCPU *cpu = ARM_CPU(cs); >> CPUARMState *env = &cpu->env; >> unsigned int new_el = env->exception.target_el; >> - target_ulong addr = env->cp15.vbar_el[new_el]; >> + vaddr addr = env->cp15.vbar_el[new_el]; > > Why not directly use the symbol type (uint64_t)? Anyway, > Nothing in particular, I was just in the mood following patch 17. vbar_el is an address, so it makes more sense to use vaddr. > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (19 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:17 ` Richard Henderson 2025-05-01 19:29 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier ` (11 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier associated define_arm_cp_regs are guarded by "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm target (32 bit). Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 595d9334977..1db40caec38 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6591,7 +6591,6 @@ static const ARMCPRegInfo zcr_reginfo[] = { .writefn = zcr_write, .raw_writefn = raw_write }, }; -#ifdef TARGET_AARCH64 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -6825,7 +6824,6 @@ static const ARMCPRegInfo nmi_reginfo[] = { .writefn = aa64_allint_write, .readfn = aa64_allint_read, .resetfn = arm_cp_reset_ignore }, }; -#endif /* TARGET_AARCH64 */ static void define_pmu_regs(ARMCPU *cpu) { @@ -7017,7 +7015,6 @@ static const ARMCPRegInfo lor_reginfo[] = { .type = ARM_CP_CONST, .resetvalue = 0 }, }; -#ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -7510,8 +7507,6 @@ static const ARMCPRegInfo nv2_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.vncr_el2) }, }; -#endif /* TARGET_AARCH64 */ - static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -8952,7 +8947,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sme, cpu)) { define_arm_cp_regs(cpu, sme_reginfo); } @@ -9013,7 +9007,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_nmi, cpu)) { define_arm_cp_regs(cpu, nmi_reginfo); } -#endif if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration 2025-05-01 6:23 ` [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier @ 2025-05-01 15:17 ` Richard Henderson 2025-05-01 19:29 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:17 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > associated define_arm_cp_regs are guarded by > "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm > target (32 bit). > > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 7 ------- > 1 file changed, 7 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration 2025-05-01 6:23 ` [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier 2025-05-01 15:17 ` Richard Henderson @ 2025-05-01 19:29 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:29 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > associated define_arm_cp_regs are guarded by > "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm > target (32 bit). > > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 7 ------- > 1 file changed, 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (20 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:19 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) Pierrick Bouvier ` (10 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which we can expose safely. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/helper.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1db40caec38..1dd9035f47e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6566,9 +6566,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ new_len = sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } @@ -10645,9 +10643,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ -#ifdef TARGET_AARCH64 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); -#endif } if (cur_el < new_el) { @@ -11552,7 +11548,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, *cs_base = flags.flags2; } -#ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the * implementation is allowed to zero the previously inaccessible @@ -11664,12 +11659,9 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { -#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); -#endif } } -#endif #ifndef CONFIG_USER_ONLY ARMSecuritySpace arm_security_space(CPUARMState *env) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 2025-05-01 6:23 ` [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier @ 2025-05-01 15:19 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:19 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which > we can expose safely. > > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/helper.c | 8 -------- > 1 file changed, 8 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (21 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:19 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 24/33] target/arm/vfp_fpscr: " Pierrick Bouvier ` (9 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 48a6bf59353..c8c80c3f969 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'helper.c', 'vfp_fpscr.c', )) arm_ss.add(zlib) @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( )) arm_user_ss.add(files( 'debug_helper.c', + 'helper.c', )) arm_common_system_ss.add(files('cpu.c'), capstone) @@ -39,6 +39,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'debug_helper.c', + 'helper.c', )) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) 2025-05-01 6:23 ` [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-01 15:19 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:19 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 24/33] target/arm/vfp_fpscr: compile file twice (user, system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (22 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:22 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier ` (8 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index c8c80c3f969..06d479570e2 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,7 +2,6 @@ arm_ss = ss.source_set() arm_common_ss = ss.source_set() arm_ss.add(files( 'gdbstub.c', - 'vfp_fpscr.c', )) arm_ss.add(zlib) @@ -32,6 +31,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_user_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) arm_common_system_ss.add(files('cpu.c'), capstone) @@ -40,6 +40,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_common_system_ss.add(files( 'debug_helper.c', 'helper.c', + 'vfp_fpscr.c', )) subdir('hvf') -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 24/33] target/arm/vfp_fpscr: compile file twice (user, system) 2025-05-01 6:23 ` [PATCH v3 24/33] target/arm/vfp_fpscr: " Pierrick Bouvier @ 2025-05-01 15:22 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:22 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (23 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 24/33] target/arm/vfp_fpscr: " Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:23 ` Richard Henderson 2025-05-01 19:30 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) Pierrick Bouvier ` (7 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Associated code is protected by cpu_isar_feature(aa64*) Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/arch_dump.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index c40df4e7fd7..1dd79849c13 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -143,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, return 0; } -#ifdef TARGET_AARCH64 static off_t sve_zreg_offset(uint32_t vq, int n) { off_t off = sizeof(struct aarch64_user_sve_header); @@ -231,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunction f, return 0; } -#endif int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) @@ -273,11 +271,9 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, return ret; } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { ret = aarch64_write_elf64_sve(f, env, cpuid, s); } -#endif return ret; } @@ -451,11 +447,9 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) if (class == ELFCLASS64) { note_size = AARCH64_PRSTATUS_NOTE_SIZE; note_size += AARCH64_PRFPREG_NOTE_SIZE; -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env); } -#endif } else { note_size = ARM_PRSTATUS_NOTE_SIZE; if (cpu_isar_feature(aa32_vfp_simd, cpu)) { -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-01 6:23 ` [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier @ 2025-05-01 15:23 ` Richard Henderson 2025-05-01 19:30 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:23 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Associated code is protected by cpu_isar_feature(aa64*) > > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/arch_dump.c | 6 ------ > 1 file changed, 6 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-01 6:23 ` [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier 2025-05-01 15:23 ` Richard Henderson @ 2025-05-01 19:30 ` Philippe Mathieu-Daudé 2025-05-03 22:26 ` Pierrick Bouvier 1 sibling, 1 reply; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:30 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Associated code is protected by cpu_isar_feature(aa64*) > > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/arch_dump.c | 6 ------ > 1 file changed, 6 deletions(-) Should we assert() in the callees? Anyway, Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals 2025-05-01 19:30 ` Philippe Mathieu-Daudé @ 2025-05-03 22:26 ` Pierrick Bouvier 0 siblings, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:26 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:30 PM, Philippe Mathieu-Daudé wrote: > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Associated code is protected by cpu_isar_feature(aa64*) >> >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/arch_dump.c | 6 ------ >> 1 file changed, 6 deletions(-) > > Should we assert() in the callees? Anyway, > I don't think so, as call sites are guarded by cpu_isar_feature(aa64_*). I understand your repeated question on this topic, and I think a good guideline could be to assert only when there are several call sites, or call sites external to compilation units. For a static function called in a single place, the risk to introduce a regression is quite low. > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (24 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:23 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 27/33] target/arm/arm-powerctl: " Pierrick Bouvier ` (6 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 06d479570e2..95a2b077dd6 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( - 'arch_dump.c', 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( + 'arch_dump.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) Pierrick Bouvier @ 2025-05-01 15:23 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:23 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 27/33] target/arm/arm-powerctl: compile file once (system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (25 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 28/33] target/arm/cortex-regs: " Pierrick Bouvier ` (5 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 95a2b077dd6..7db573f4a97 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( - 'arm-powerctl.c', 'arm-qmp-cmds.c', 'cortex-regs.c', 'machine.c', @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(files( 'arch_dump.c', + 'arm-powerctl.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 27/33] target/arm/arm-powerctl: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 27/33] target/arm/arm-powerctl: " Pierrick Bouvier @ 2025-05-01 15:24 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:24 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 28/33] target/arm/cortex-regs: compile file once (system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (26 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 27/33] target/arm/arm-powerctl: " Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:30 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t Pierrick Bouvier ` (4 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 7db573f4a97..6e0327b6f5b 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -16,7 +16,6 @@ arm_system_ss = ss.source_set() arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', - 'cortex-regs.c', 'machine.c', 'ptw.c', )) @@ -38,6 +37,7 @@ arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cortex-regs.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 28/33] target/arm/cortex-regs: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 28/33] target/arm/cortex-regs: " Pierrick Bouvier @ 2025-05-01 15:30 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:30 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (27 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 28/33] target/arm/cortex-regs: " Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 15:32 ` Richard Henderson 2025-05-01 19:35 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw Pierrick Bouvier ` (3 subsequent siblings) 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d0a53d0987f..424d1b54275 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size; + uint64_t page_size; uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * validation to do here. */ if (inputsize < addrsize) { - target_ulong top_bits = sextract64(address, inputsize, + uint64_t top_bits = sextract64(address, inputsize, addrsize - inputsize); if (-top_bits != param.select) { /* The gap between the two regions is a Translation fault */ -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t 2025-05-01 6:23 ` [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t Pierrick Bouvier @ 2025-05-01 15:32 ` Richard Henderson 2025-05-01 19:35 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 15:32 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/ptw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index d0a53d0987f..424d1b54275 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > uint64_t ttbr; > hwaddr descaddr, indexmask, indexmask_grainsize; > uint32_t tableattrs; > - target_ulong page_size; > + uint64_t page_size; > uint64_t attrs; > int32_t stride; > int addrsize, inputsize, outputsize; > @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > * validation to do here. > */ > if (inputsize < addrsize) { > - target_ulong top_bits = sextract64(address, inputsize, > + uint64_t top_bits = sextract64(address, inputsize, > addrsize - inputsize); > if (-top_bits != param.select) { > /* The gap between the two regions is a Translation fault */ Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t 2025-05-01 6:23 ` [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t Pierrick Bouvier 2025-05-01 15:32 ` Richard Henderson @ 2025-05-01 19:35 ` Philippe Mathieu-Daudé 2025-05-01 21:14 ` Richard Henderson 2025-05-03 22:35 ` Pierrick Bouvier 1 sibling, 2 replies; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:35 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/ptw.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index d0a53d0987f..424d1b54275 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > uint64_t ttbr; > hwaddr descaddr, indexmask, indexmask_grainsize; > uint32_t tableattrs; > - target_ulong page_size; > + uint64_t page_size; Alternatively size_t. > uint64_t attrs; > int32_t stride; > int addrsize, inputsize, outputsize; > @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, > * validation to do here. > */ > if (inputsize < addrsize) { > - target_ulong top_bits = sextract64(address, inputsize, > + uint64_t top_bits = sextract64(address, inputsize, > addrsize - inputsize); Maybe use int64_t for signed? Anyway, pre-existing, so: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > if (-top_bits != param.select) { > /* The gap between the two regions is a Translation fault */ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t 2025-05-01 19:35 ` Philippe Mathieu-Daudé @ 2025-05-01 21:14 ` Richard Henderson 2025-05-03 22:35 ` Pierrick Bouvier 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 21:14 UTC (permalink / raw) To: Philippe Mathieu-Daudé, Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:35, Philippe Mathieu-Daudé wrote: > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/ptw.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >> index d0a53d0987f..424d1b54275 100644 >> --- a/target/arm/ptw.c >> +++ b/target/arm/ptw.c >> @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> uint64_t ttbr; >> hwaddr descaddr, indexmask, indexmask_grainsize; >> uint32_t tableattrs; >> - target_ulong page_size; >> + uint64_t page_size; > > Alternatively size_t. No, this is not related to the size of any host-side object. Bear in mind this particular page_size is used for the sizes of the intermediate page table levels. So, at the very top level of the page table walk this will be quite large. r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t 2025-05-01 19:35 ` Philippe Mathieu-Daudé 2025-05-01 21:14 ` Richard Henderson @ 2025-05-03 22:35 ` Pierrick Bouvier 1 sibling, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:35 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 5/1/25 12:35 PM, Philippe Mathieu-Daudé wrote: > On 1/5/25 08:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/ptw.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >> index d0a53d0987f..424d1b54275 100644 >> --- a/target/arm/ptw.c >> +++ b/target/arm/ptw.c >> @@ -1660,7 +1660,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> uint64_t ttbr; >> hwaddr descaddr, indexmask, indexmask_grainsize; >> uint32_t tableattrs; >> - target_ulong page_size; >> + uint64_t page_size; > > Alternatively size_t. > >> uint64_t attrs; >> int32_t stride; >> int addrsize, inputsize, outputsize; >> @@ -1733,7 +1733,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> * validation to do here. >> */ >> if (inputsize < addrsize) { >> - target_ulong top_bits = sextract64(address, inputsize, >> + uint64_t top_bits = sextract64(address, inputsize, >> addrsize - inputsize); > > Maybe use int64_t for signed? Anyway, pre-existing, so: > Yes, I'll change to signed integer. > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > >> if (-top_bits != param.select) { >> /* The gap between the two regions is a Translation fault */ > ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (28 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 31/33] target/arm/ptw: compile file once (system) Pierrick Bouvier ` (2 subsequent siblings) 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/ptw.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 424d1b54275..f428c9b9267 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -737,7 +737,14 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) +#ifndef CONFIG_TCG + /* non-TCG guests only use debug-mode. */ + g_assert_not_reached(); +#endif + + /* AArch32 does not have FEAT_HADFS */ + g_assert(arm_feature(env, ARM_FEATURE_AARCH64)); + uint64_t cur_val; void *host = ptw->out_host; @@ -851,10 +858,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, cur_val = le64_to_cpu(cur_val); } return cur_val; -#else - /* AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode. */ - g_assert_not_reached(); -#endif } static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw 2025-05-01 6:23 ` [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw Pierrick Bouvier @ 2025-05-01 16:24 ` Richard Henderson 2025-05-03 22:38 ` Pierrick Bouvier 2025-05-03 22:48 ` Pierrick Bouvier 0 siblings, 2 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 16:24 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/ptw.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 424d1b54275..f428c9b9267 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -737,7 +737,14 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, > uint64_t new_val, S1Translate *ptw, > ARMMMUFaultInfo *fi) > { > -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) > +#ifndef CONFIG_TCG > + /* non-TCG guests only use debug-mode. */ > + g_assert_not_reached(); > +#endif > + > + /* AArch32 does not have FEAT_HADFS */ > + g_assert(arm_feature(env, ARM_FEATURE_AARCH64)); > + I don't think we need an assert here. The ifdef for aarch64 also protects the qatomic_cmpxchg__nocheck below, because aarch64 guest can only be built with a 64-bit host. Are we still able to build qemu-system-arm on a 32-bit host with these changes? It may be tricky to check, because the two easiest 32-bit hosts (i686, armv7) also happen to have a 64-bit cmpxchg. I think "make docker-test-build@debian-mipsel-cross" will be the right test. If that fails, I think you could s/TARGET_AARCH64/CONFIG_ATOMIC64/ here. r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw 2025-05-01 16:24 ` Richard Henderson @ 2025-05-03 22:38 ` Pierrick Bouvier 2025-05-03 22:48 ` Pierrick Bouvier 1 sibling, 0 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:38 UTC (permalink / raw) To: Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/1/25 9:24 AM, Richard Henderson wrote: > On 4/30/25 23:23, Pierrick Bouvier wrote: >> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> >> --- >> target/arm/ptw.c | 13 ++++++++----- >> 1 file changed, 8 insertions(+), 5 deletions(-) >> >> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >> index 424d1b54275..f428c9b9267 100644 >> --- a/target/arm/ptw.c >> +++ b/target/arm/ptw.c >> @@ -737,7 +737,14 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, >> uint64_t new_val, S1Translate *ptw, >> ARMMMUFaultInfo *fi) >> { >> -#if defined(TARGET_AARCH64) && defined(CONFIG_TCG) >> +#ifndef CONFIG_TCG >> + /* non-TCG guests only use debug-mode. */ >> + g_assert_not_reached(); >> +#endif >> + >> + /* AArch32 does not have FEAT_HADFS */ >> + g_assert(arm_feature(env, ARM_FEATURE_AARCH64)); >> + > > I don't think we need an assert here. > > The ifdef for aarch64 also protects the qatomic_cmpxchg__nocheck below, because aarch64 > guest can only be built with a 64-bit host. > > Are we still able to build qemu-system-arm on a 32-bit host with these changes? It may be > tricky to check, because the two easiest 32-bit hosts (i686, armv7) also happen to have a > 64-bit cmpxchg. I think "make docker-test-build@debian-mipsel-cross" will be the right test. > Good catch. I was indeed building only with i686. I'll add mipsel instead. /usr/lib/gcc-cross/mipsel-linux-gnu/12/../../../../mipsel-linux-gnu/bin/ld: libtarget_system_arm.a.p/target_arm_ptw.c.o: undefined reference to symbol '__atomic_compare_exchange_8@@LIBATOMIC_1.0' > If that fails, I think you could s/TARGET_AARCH64/CONFIG_ATOMIC64/ here. > I'll revert this change and simply do this replace, adding a comment as well. > > r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw 2025-05-01 16:24 ` Richard Henderson 2025-05-03 22:38 ` Pierrick Bouvier @ 2025-05-03 22:48 ` Pierrick Bouvier 2025-05-04 15:52 ` Richard Henderson 1 sibling, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-03 22:48 UTC (permalink / raw) To: Richard Henderson, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/1/25 9:24 AM, Richard Henderson wrote: > Are we still able to build qemu-system-arm on a 32-bit host with these changes? It may be > tricky to check, because the two easiest 32-bit hosts (i686, armv7) also happen to have a > 64-bit cmpxchg. I think "make docker-test-build@debian-mipsel-cross" will be the right test. By the way, I'm usually using debian-s390x-cross for testing a HOST_BIG_ENDIAN build. Is that the best choice available? ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw 2025-05-03 22:48 ` Pierrick Bouvier @ 2025-05-04 15:52 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-04 15:52 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 5/3/25 15:48, Pierrick Bouvier wrote: > On 5/1/25 9:24 AM, Richard Henderson wrote: >> Are we still able to build qemu-system-arm on a 32-bit host with these changes? It may be >> tricky to check, because the two easiest 32-bit hosts (i686, armv7) also happen to have a >> 64-bit cmpxchg. I think "make docker-test-build@debian-mipsel-cross" will be the right >> test. > > By the way, I'm usually using debian-s390x-cross for testing a HOST_BIG_ENDIAN build. Is > that the best choice available? Yes. r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 31/33] target/arm/ptw: compile file once (system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (29 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6e0327b6f5b..151184da71c 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -17,7 +17,6 @@ arm_common_system_ss = ss.source_set() arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', - 'ptw.c', )) arm_user_ss = ss.source_set() @@ -40,6 +39,7 @@ arm_common_system_ss.add(files( 'cortex-regs.c', 'debug_helper.c', 'helper.c', + 'ptw.c', 'vfp_fpscr.c', )) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 31/33] target/arm/ptw: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 31/33] target/arm/ptw: compile file once (system) Pierrick Bouvier @ 2025-05-01 16:24 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 16:24 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (30 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 31/33] target/arm/ptw: compile file once (system) Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier 32 siblings, 1 reply; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 151184da71c..29a36fb3c5e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,9 +5,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) -arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c')) @@ -18,6 +15,8 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_user_ss = ss.source_set() arm_user_ss.add(files('cpu.c')) -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode 2025-05-01 6:23 ` [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier @ 2025-05-01 16:24 ` Richard Henderson 0 siblings, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 16:24 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier ` (31 preceding siblings ...) 2025-05-01 6:23 ` [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier @ 2025-05-01 6:23 ` Pierrick Bouvier 2025-05-01 16:25 ` Richard Henderson 2025-05-01 19:36 ` Philippe Mathieu-Daudé 32 siblings, 2 replies; 79+ messages in thread From: Pierrick Bouvier @ 2025-05-01 6:23 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm, Pierrick Bouvier Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> --- target/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 29a36fb3c5e..bb1c09676d5 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -15,7 +15,7 @@ arm_system_ss.add(files( 'arm-qmp-cmds.c', 'machine.c', )) -arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) +arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_user_ss = ss.source_set() @@ -32,6 +32,7 @@ arm_user_ss.add(files( arm_common_system_ss.add(files('cpu.c'), capstone) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) +arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', -- 2.47.2 ^ permalink raw reply related [flat|nested] 79+ messages in thread
* Re: [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier @ 2025-05-01 16:25 ` Richard Henderson 2025-05-01 19:36 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Richard Henderson @ 2025-05-01 16:25 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, alex.bennee, Paolo Bonzini, anjo, Philippe Mathieu-Daudé, kvm On 4/30/25 23:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier<pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 79+ messages in thread
* Re: [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) 2025-05-01 6:23 ` [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier 2025-05-01 16:25 ` Richard Henderson @ 2025-05-01 19:36 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 79+ messages in thread From: Philippe Mathieu-Daudé @ 2025-05-01 19:36 UTC (permalink / raw) To: Pierrick Bouvier, qemu-devel Cc: Peter Maydell, qemu-arm, richard.henderson, alex.bennee, Paolo Bonzini, anjo, kvm On 1/5/25 08:23, Pierrick Bouvier wrote: > Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> > --- > target/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 79+ messages in thread
end of thread, other threads:[~2025-05-04 15:52 UTC | newest] Thread overview: 79+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-05-01 6:23 [PATCH v3 00/33] single-binary: compile target/arm twice Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 01/33] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 02/33] include/system/hvf: missing vaddr include Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 03/33] meson: add common libs for target and target_system Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 04/33] target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.h Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 05/33] target/arm/kvm-stub: add kvm_arm_reset_vcpu stub Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 06/33] target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.c Pierrick Bouvier 2025-05-01 19:04 ` Philippe Mathieu-Daudé 2025-05-03 21:12 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 07/33] accel/hvf: add hvf_enabled() for common code Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 08/33] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 09/33] target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state common Pierrick Bouvier 2025-05-01 19:06 ` Philippe Mathieu-Daudé 2025-05-03 21:18 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 10/33] target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_features Pierrick Bouvier 2025-05-01 19:06 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 11/33] target/arm/cpu: compile file twice (user, system) only Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 12/33] target/arm/cpu32-stubs.c: compile file twice (user, system) Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 13/33] target/arm/helper: use i64 for exception_pc_alignment Pierrick Bouvier 2025-05-01 15:02 ` Richard Henderson 2025-05-01 16:30 ` Richard Henderson 2025-05-03 21:54 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 14/33] target/arm/helper: user i64 for probe_access Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 15/33] target/arm/helper: extract common helpers Pierrick Bouvier 2025-05-01 15:06 ` Richard Henderson 2025-05-01 15:24 ` Pierrick Bouvier 2025-05-03 22:11 ` Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 16/33] target/arm/debug_helper: only include " Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 17/33] target/arm/debug_helper: remove target_ulong Pierrick Bouvier 2025-05-01 15:07 ` Richard Henderson 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-03 22:16 ` Pierrick Bouvier 2025-05-01 19:26 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 18/33] target/arm/debug_helper: compile file twice (user, system) Pierrick Bouvier 2025-05-01 15:14 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 19/33] target/arm/helper: restrict include to common helpers Pierrick Bouvier 2025-05-01 15:15 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 20/33] target/arm/helper: replace target_ulong by vaddr Pierrick Bouvier 2025-05-01 15:15 ` Richard Henderson 2025-05-01 19:28 ` Philippe Mathieu-Daudé 2025-05-03 22:20 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 21/33] target/arm/helper: expose aarch64 cpu registration Pierrick Bouvier 2025-05-01 15:17 ` Richard Henderson 2025-05-01 19:29 ` Philippe Mathieu-Daudé 2025-05-01 6:23 ` [PATCH v3 22/33] target/arm/helper: remove remaining TARGET_AARCH64 Pierrick Bouvier 2025-05-01 15:19 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 23/33] target/arm/helper: compile file twice (user, system) Pierrick Bouvier 2025-05-01 15:19 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 24/33] target/arm/vfp_fpscr: " Pierrick Bouvier 2025-05-01 15:22 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 25/33] target/arm/arch_dump: remove TARGET_AARCH64 conditionals Pierrick Bouvier 2025-05-01 15:23 ` Richard Henderson 2025-05-01 19:30 ` Philippe Mathieu-Daudé 2025-05-03 22:26 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 26/33] target/arm/arch_dump: compile file once (system) Pierrick Bouvier 2025-05-01 15:23 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 27/33] target/arm/arm-powerctl: " Pierrick Bouvier 2025-05-01 15:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 28/33] target/arm/cortex-regs: " Pierrick Bouvier 2025-05-01 15:30 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 29/33] target/arm/ptw: replace target_ulong with uint64_t Pierrick Bouvier 2025-05-01 15:32 ` Richard Henderson 2025-05-01 19:35 ` Philippe Mathieu-Daudé 2025-05-01 21:14 ` Richard Henderson 2025-05-03 22:35 ` Pierrick Bouvier 2025-05-01 6:23 ` [PATCH v3 30/33] target/arm/ptw: remove TARGET_AARCH64 from arm_casq_ptw Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-03 22:38 ` Pierrick Bouvier 2025-05-03 22:48 ` Pierrick Bouvier 2025-05-04 15:52 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 31/33] target/arm/ptw: compile file once (system) Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 32/33] target/arm/meson: accelerator files are not needed in user mode Pierrick Bouvier 2025-05-01 16:24 ` Richard Henderson 2025-05-01 6:23 ` [PATCH v3 33/33] target/arm/kvm-stub: compile file once (system) Pierrick Bouvier 2025-05-01 16:25 ` Richard Henderson 2025-05-01 19:36 ` Philippe Mathieu-Daudé
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).