Re: [PATCH 3/3] target/ppc: Add ISA v3.1 variants of sync instruction

[Chinmay Rath <rathc@linux.vnet.ibm.com>]

On 5/1/24 18:34, Nicholas Piggin wrote:
> POWER10 adds a new field to sync for store-store syncs, and some
> new variants of the existing syncs that include persistent memory.
>
> Implement the store-store syncs and plwsync/phwsync.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
> ---
>   target/ppc/insn32.decode             |  6 ++--
>   target/ppc/translate/misc-impl.c.inc | 41 ++++++++++++++++++++--------
>   2 files changed, 32 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 6b89804b15..a180380750 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -1001,7 +1001,7 @@ MSGSYNC         011111 ----- ----- ----- 1101110110 -
>   
>   # Memory Barrier Instructions
>   
> -&X_sync         l
> -@X_sync         ...... ... l:2 ..... ..... .......... .           &X_sync
> -SYNC            011111 --- ..  ----- ----- 1001010110 -           @X_sync
> +&X_sync         l sc
> +@X_sync         ...... .. l:3 ... sc:2 ..... .......... .           &X_sync
> +SYNC            011111 -- ... --- ..   ----- 1001010110 -           @X_sync
>   EIEIO           011111 ----- ----- ----- 1101010110 -
> diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/misc-impl.c.inc
> index 9226467f81..3467b49d0d 100644
> --- a/target/ppc/translate/misc-impl.c.inc
> +++ b/target/ppc/translate/misc-impl.c.inc
> @@ -25,6 +25,7 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
>   {
>       TCGBar bar = TCG_MO_ALL;
>       uint32_t l = a->l;
> +    uint32_t sc = a->sc;
>   
>       /*
>        * BookE uses the msync mnemonic. This means hwsync, except in the
> @@ -46,20 +47,36 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
>           gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
>       }
>   
> -    if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
> -        bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
> -    }
> -
>       /*
> -     * We may need to check for a pending TLB flush.
> -     *
> -     * We do this on ptesync (l == 2) on ppc64 and any sync on ppc32.
> -     *
> -     * Additionally, this can only happen in kernel mode however so
> -     * check MSR_PR as well.
> +     * In ISA v3.1, the L field grew one bit. Mask that out to ignore it in
> +     * older processors. It also added the SC field, zero this to ignore
> +     * it too.
>        */
> -    if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
> -        gen_check_tlb_flush(ctx, true);
> +    if (!(ctx->insns_flags2 & PPC2_ISA310)) {
> +        l &= 0x3;
> +        sc = 0;
> +    }
> +
> +    if (sc) {
> +        /* Store syncs [stsync, stcisync, stncisync]. These ignore L. */
> +        bar = TCG_MO_ST_ST;
> +    } else {
> +        if (((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) || (l == 5)) {
> +            /* lwsync, or plwsync on POWER10 and later */
> +            bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
> +        }
> +
> +        /*
> +         * We may need to check for a pending TLB flush.
> +         *
> +         * We do this on ptesync (l == 2) on ppc64 and any sync on ppc32.
> +         *
> +         * Additionally, this can only happen in kernel mode however so
> +         * check MSR_PR as well.
> +         */
> +        if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
> +            gen_check_tlb_flush(ctx, true);
> +        }
>       }
>   
>       tcg_gen_mb(bar | TCG_BAR_SC);