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Tue, 7 May 2024 07:09:03 +0000 (GMT) Message-ID: <2bd50388-2bb0-42c5-a2ce-8c243c2051dd@linux.vnet.ibm.com> Date: Tue, 7 May 2024 12:39:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] target/ppc: Add ISA v3.1 variants of sync instruction Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , Chinmay Rath References: <20240501130435.941189-1-npiggin@gmail.com> <20240501130435.941189-4-npiggin@gmail.com> From: Chinmay Rath In-Reply-To: <20240501130435.941189-4-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4xCsf_1LuHEPIoC6UMIXiaAC5esIjp6t X-Proofpoint-ORIG-GUID: Smhv1pXMGR8wUzI0TIJKy3iH-9hEdfUf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-07_02,2024-05-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 suspectscore=0 mlxlogscore=967 adultscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2405070048 Received-SPF: none client-ip=148.163.156.1; envelope-from=rathc@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/1/24 18:34, Nicholas Piggin wrote: > POWER10 adds a new field to sync for store-store syncs, and some > new variants of the existing syncs that include persistent memory. > > Implement the store-store syncs and plwsync/phwsync. > > Signed-off-by: Nicholas Piggin Reviewed-by: Chinmay Rath > --- > target/ppc/insn32.decode | 6 ++-- > target/ppc/translate/misc-impl.c.inc | 41 ++++++++++++++++++++-------- > 2 files changed, 32 insertions(+), 15 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 6b89804b15..a180380750 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -1001,7 +1001,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - > > # Memory Barrier Instructions > > -&X_sync l > -@X_sync ...... ... l:2 ..... ..... .......... . &X_sync > -SYNC 011111 --- .. ----- ----- 1001010110 - @X_sync > +&X_sync l sc > +@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync > +SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync > EIEIO 011111 ----- ----- ----- 1101010110 - > diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/misc-impl.c.inc > index 9226467f81..3467b49d0d 100644 > --- a/target/ppc/translate/misc-impl.c.inc > +++ b/target/ppc/translate/misc-impl.c.inc > @@ -25,6 +25,7 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a) > { > TCGBar bar = TCG_MO_ALL; > uint32_t l = a->l; > + uint32_t sc = a->sc; > > /* > * BookE uses the msync mnemonic. This means hwsync, except in the > @@ -46,20 +47,36 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a) > gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); > } > > - if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { > - bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; > - } > - > /* > - * We may need to check for a pending TLB flush. > - * > - * We do this on ptesync (l == 2) on ppc64 and any sync on ppc32. > - * > - * Additionally, this can only happen in kernel mode however so > - * check MSR_PR as well. > + * In ISA v3.1, the L field grew one bit. Mask that out to ignore it in > + * older processors. It also added the SC field, zero this to ignore > + * it too. > */ > - if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { > - gen_check_tlb_flush(ctx, true); > + if (!(ctx->insns_flags2 & PPC2_ISA310)) { > + l &= 0x3; > + sc = 0; > + } > + > + if (sc) { > + /* Store syncs [stsync, stcisync, stncisync]. These ignore L. */ > + bar = TCG_MO_ST_ST; > + } else { > + if (((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) || (l == 5)) { > + /* lwsync, or plwsync on POWER10 and later */ > + bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; > + } > + > + /* > + * We may need to check for a pending TLB flush. > + * > + * We do this on ptesync (l == 2) on ppc64 and any sync on ppc32. > + * > + * Additionally, this can only happen in kernel mode however so > + * check MSR_PR as well. > + */ > + if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { > + gen_check_tlb_flush(ctx, true); > + } > } > > tcg_gen_mb(bar | TCG_BAR_SC);