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From: Artyom Tarasenko <atar4qemu@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	Richard Henderson <rth@twiddle.net>,
	Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v2 23/30] target-sparc: implement auto-demapping for UA2005 CPUs
Date: Wed, 11 Jan 2017 21:19:54 +0100	[thread overview]
Message-ID: <2bf424bff7e4dee34fcbcada4fd490205f392823.1484165352.git.atar4qemu@gmail.com> (raw)
In-Reply-To: <cover.1484165352.git.atar4qemu@gmail.com>
In-Reply-To: <cover.1484165352.git.atar4qemu@gmail.com>

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 target/sparc/ldst_helper.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 0447d4e..57b3b97 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -210,6 +210,28 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
 {
     unsigned int i, replace_used;
 
+    if (cpu_has_hypervisor(env1)) {
+        uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
+        uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
+        uint32_t new_ctx = tlb_tag & 0x1fffU;
+        for (i = 0; i < 64; i++) {
+            uint32_t ctx = tlb[i].tag & 0x1fffU;
+            /* check if new mapping overlaps an existing one */
+            if (new_ctx == ctx) {
+                uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
+                uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
+                if (new_vaddr == vaddr
+                    || (new_vaddr < vaddr + size
+                        && vaddr < new_vaddr + new_size)) {
+                    DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
+                                new_vaddr);
+                    replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
+                    return;
+                }
+            }
+
+        }
+    }
     /* Try replacing invalid entry */
     for (i = 0; i < 64; i++) {
         if (!TTE_IS_VALID(tlb[i].tte)) {
-- 
1.8.3.1

  parent reply	other threads:[~2017-01-11 20:21 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-11 20:19 [Qemu-devel] [PATCH v2 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 02/30] target-sparc: store cpu super- and hypervisor flags in TB Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 03/30] target-sparc: use explicit mmu register pointers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 04/30] target-sparc: add UA2005 TTE bit #defines Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 05/30] target-sparc: add UltraSPARC T1 TLB #defines Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 08/30] target-sparc: implement UA2005 scratchpad registers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 10/30] target-sparc: hypervisor mode takes over nucleus mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 12/30] target-sparc: implement UA2005 GL register Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 14/30] target-sparc: fix immediate UA2005 traps Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 15/30] target-sparc: use direct address translation in hyperprivileged mode Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 16/30] target-sparc: allow priveleged ASIs " Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 18/30] target-sparc: replace the last tlb entry when no free entries left Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 20/30] target-sparc: implement UA2005 TSB Pointers Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 21/30] target-sparc: simplify ultrasparc_tsb_pointer Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 22/30] target-sparc: allow 256M sized pages Artyom Tarasenko
2017-01-11 20:19 ` Artyom Tarasenko [this message]
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 24/30] target-sparc: add more registers to dump_mmu Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Artyom Tarasenko
2017-01-11 20:19 ` [Qemu-devel] [PATCH v2 28/30] target-sparc: implement sun4v RTC Artyom Tarasenko
2017-01-11 20:20 ` [Qemu-devel] [PATCH v2 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Artyom Tarasenko
2017-01-11 20:20 ` [Qemu-devel] [PATCH v2 30/30] target-sparc: fix up niagara machine Artyom Tarasenko
2017-01-26  7:35   ` Markus Armbruster
2017-01-26  9:33     ` Artyom Tarasenko
2017-01-27 14:06       ` Markus Armbruster
2017-01-27 14:27         ` Paolo Bonzini
2017-01-27 14:57           ` Artyom Tarasenko

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