From: Tony Nguyen <tony.nguyen.git@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tony Nguyen <tony.nguyen.git@gmail.com>,
Tony Nguyen <tony.nguyen@bt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v8 18/21] cpu: TLB_FLAGS_MASK bit to force memory slow path
Date: Thu, 22 Aug 2019 01:09:12 +1000 [thread overview]
Message-ID: <2c13e85942fa740953fd5ceee6f65f854dc9b8de.1566397711.git.tony.nguyen.git@gmail.com> (raw)
In-Reply-To: <cover.1566397711.git.tony.nguyen.git@gmail.com>
The fast path is taken when TLB_FLAGS_MASK is all zero.
TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,
there are no other side effects.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 536ea58f81..e496f9900f 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3))
/* Set if TLB entry must have MMU lookup repeated for every access */
#define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4))
+/* Set if TLB entry must take the slow path. */
+#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5))
/* Use this mask to check interception with an alignment mask
* in a TCG backend.
*/
-#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
- | TLB_RECHECK)
+#define TLB_FLAGS_MASK \
+ (TLB_INVALID_MASK \
+ | TLB_NOTDIRTY \
+ | TLB_MMIO \
+ | TLB_RECHECK \
+ | TLB_FORCE_SLOW)
/**
* tlb_hit_page: return true if page aligned @addr is a hit against the
--
2.23.0
next prev parent reply other threads:[~2019-08-21 15:16 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1566397711.git.tony.nguyen.git@gmail.com>
2019-08-21 15:08 ` [Qemu-devel] [PATCH v8 01/21] configure: Define TARGET_ALIGNED_ONLY in configure Tony Nguyen
2019-08-22 0:22 ` Richard Henderson
2019-08-21 15:08 ` [Qemu-devel] [PATCH v8 02/21] tcg: TCGMemOp is now accelerator independent MemOp Tony Nguyen
2019-08-21 15:08 ` [Qemu-devel] [PATCH v8 03/21] memory: Introduce size_memop Tony Nguyen
2019-08-21 15:08 ` [Qemu-devel] [PATCH v8 04/21] target/mips: Access MemoryRegion with MemOp Tony Nguyen
2019-08-21 16:50 ` [Qemu-devel] [EXTERNAL] " Aleksandar Markovic
2019-08-21 15:08 ` [Qemu-devel] [PATCH v8 05/21] hw/s390x: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 06/21] hw/intc/armv7m_nic: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 07/21] hw/virtio: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 08/21] hw/vfio: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 09/21] exec: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 10/21] cputlb: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 11/21] memory: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 12/21] hw/s390x: Hard code size with MO_{8|16|32|64} Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 13/21] target/mips: " Tony Nguyen
2019-08-21 16:48 ` [Qemu-devel] [EXTERNAL] " Aleksandar Markovic
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 14/21] exec: " Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 16/21] cputlb: Replace size and endian operands for MemOp Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 17/21] memory: Single byte swap along the I/O path Tony Nguyen
2019-08-21 15:09 ` Tony Nguyen [this message]
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 19/21] cputlb: Byte swap memory transaction attribute Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 20/21] target/sparc: Add TLB entry with attributes Tony Nguyen
2019-08-21 15:09 ` [Qemu-devel] [PATCH v8 21/21] target/sparc: sun4u Invert Endian TTE bit Tony Nguyen
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