From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bfjS1-0002KH-JW for qemu-devel@nongnu.org; Fri, 02 Sep 2016 04:03:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bfjRy-0003gh-Cn for qemu-devel@nongnu.org; Fri, 02 Sep 2016 04:03:49 -0400 Received: from mo68.mail-out.ovh.net ([178.32.228.68]:56078) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bfjRy-0003g7-31 for qemu-devel@nongnu.org; Fri, 02 Sep 2016 04:03:46 -0400 Received: from player695.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo68.mail-out.ovh.net (Postfix) with ESMTP id 3EEA9FF9A84 for ; Fri, 2 Sep 2016 10:03:45 +0200 (CEST) References: <1472661255-20160-1-git-send-email-clg@kaod.org> <1472661255-20160-5-git-send-email-clg@kaod.org> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <2c2e5bc0-6be5-4e7c-81fb-a8e50d50e7fa@kaod.org> Date: Fri, 2 Sep 2016 10:03:39 +0200 MIME-Version: 1.0 In-Reply-To: <1472661255-20160-5-git-send-email-clg@kaod.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 4/7] ppc/pnv: add a core mask to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf On 08/31/2016 06:34 PM, C=C3=A9dric Le Goater wrote: > This will be used to build real HW ids for the cores and enforce some > limits on the available cores per chip. >=20 > Signed-off-by: C=C3=A9dric Le Goater > --- > hw/ppc/pnv.c | 27 +++++++++++++++++++++++++++ > include/hw/ppc/pnv.h | 2 ++ > 2 files changed, 29 insertions(+) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index a6e7f66b2c0a..b6efb5e3ef07 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -236,6 +236,27 @@ static void ppc_powernv_init(MachineState *machine= ) > g_free(chip_typename); > } > =20 > +/* Allowed core identifiers on a POWER8 Processor Chip : > + * > + * > + * EX1 - Venice only > + * EX2 - Venice only > + * EX3 - Venice only > + * EX4 > + * EX5 > + * EX6 > + * > + * EX9 - Venice only > + * EX10 - Venice only > + * EX11 - Venice only > + * EX12 > + * EX13 > + * EX14 > + * > + */ > +#define POWER8E_CORE_MASK (~0xffff8f8f) > +#define POWER8_CORE_MASK (~0xffff8181) > + > static void pnv_chip_power8nvl_realize(PnvChip *chip, Error **errp) > { > ; > @@ -250,6 +271,8 @@ static void pnv_chip_power8nvl_class_init(ObjectCla= ss *klass, void *data) > k->cpu_model =3D "POWER8NVL"; > k->chip_type =3D PNV_CHIP_P8NVL; > k->chip_f000f =3D 0x120d304980000000ull; > + k->cores_max =3D 12; > + k->cores_mask =3D POWER8_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8NVL"; > } > =20 > @@ -274,6 +297,8 @@ static void pnv_chip_power8_class_init(ObjectClass = *klass, void *data) > k->cpu_model =3D "POWER8"; > k->chip_type =3D PNV_CHIP_P8; > k->chip_f000f =3D 0x220ea04980000000ull; > + k->cores_max =3D 12; > + k->cores_mask =3D POWER8_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8"; > } > =20 > @@ -298,6 +323,8 @@ static void pnv_chip_power8e_class_init(ObjectClass= *klass, void *data) > k->cpu_model =3D "POWER8E"; > k->chip_type =3D PNV_CHIP_P8E; > k->chip_f000f =3D 0x221ef04980000000ull; > + k->cores_max =3D 6; > + k->cores_mask =3D POWER8E_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8E"; > } > =20 > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index bc6e1f80096b..987bc70245a7 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -49,6 +49,8 @@ typedef struct PnvChipClass { > /*< private >*/ > SysBusDeviceClass parent_class; > /*< public >*/ > + uint32_t cores_max; > + uint32_t cores_mask; This 'cores_mask' attribute needs to be a uint64_t for POWER9. The=20 core chiplet ids are in the range : [ 0x20 - 0x37 ] I will change that in the next version and include a PnvChipPower9 class as the cpu_model was merged in David's branch. Cheers, C.=20