From: Thomas Huth <thuth@redhat.com>
To: Michael Levit <michael@videogpu.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, philmd@linaro.org,
pbonzini@redhat.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com,
smishash@gmail.com
Subject: Re: [PATCH v4 0/5] RISC-V: NEORV32 CPU, peripherials, and machine
Date: Tue, 11 Nov 2025 08:13:25 +0100 [thread overview]
Message-ID: <2c58b1c2-13c7-4551-bcf7-bf214933d4af@redhat.com> (raw)
In-Reply-To: <CA+KCYksKitF6YO390y9JhHWaE2bvKw1nPJ0Axq8FvJyCgEEfqg@mail.gmail.com>
On 10/11/2025 19.46, Michael Levit wrote:
>
> Are these binaries available publically somewhere on the internet?
>
>
> Currently, as far as I know, there are no prebuilt binaries — only source
> files for the bootloader and firmware examples in the NEORV32 repository.
> I compile the binaries and prepare the flash image locally.
>
> If so,
> could you please add a test in tests/functional/riscv32 that make sure that
> the machine is basically working, so we don't face any regressions in the
> future?
>
>
> I can upload the generated image to my GitHub repository, or alternatively
> to some QEMU-related storage if there’s a preferred location?
The QEMU project does not maintain a storage for such third party binaries,
so if you could put them on your GitHub repo, that would be great!
Thanks,
Thomas
> The test image is around 4 MB, plus a few kilobytes for the bootloader.
> I will add the test of course.
>
> Thanks for the review and feedback!
>
prev parent reply other threads:[~2025-11-11 7:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-09 19:15 [PATCH v4 0/5] RISC-V: NEORV32 CPU, peripherials, and machine Michael Levit
2025-11-09 19:15 ` [PATCH v4 1/5] target/riscv: add NEORV32 RV32 CPU type and vendor CSR hooks Michael Levit
2025-11-09 19:15 ` [PATCH v4 2/5] hw/misc: add NEORV32 SYSINFO block (CLK/MISC/SOC/CACHE) Michael Levit
2025-11-09 19:15 ` [PATCH v4 3/5] hw/char: add NEORV32 UART (CTRL/DATA, fifo, chardev) Michael Levit
2025-11-13 6:41 ` Mark Cave-Ayland
2025-11-13 6:46 ` Mark Cave-Ayland
2025-11-09 19:15 ` [PATCH v4 4/5] hw/ssi: add NEORV32 SPI controller (SSI master, CS command) Michael Levit
2025-11-13 6:51 ` Mark Cave-Ayland
2025-11-09 19:15 ` [PATCH v4 5/5] hw/riscv: introduce 'neorv32' board, docs, and riscv32 device config Michael Levit
2025-11-10 12:28 ` [PATCH v4 0/5] RISC-V: NEORV32 CPU, peripherials, and machine Thomas Huth
2025-11-10 18:46 ` Michael Levit
2025-11-11 7:13 ` Thomas Huth [this message]
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