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From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Date: Tue, 3 Nov 2020 12:19:09 -0800	[thread overview]
Message-ID: <2c67bcb2-7baf-2b43-38dd-1ae83de43e85@linaro.org> (raw)
In-Reply-To: <df31a53b141fb540eeaf1ca4da1f9e7d3c2e6238.1604432950.git.alistair.francis@wdc.com>

On 11/3/20 11:50 AM, Alistair Francis wrote:
> From: Yifei Jiang <jiangyifei@huawei.com>
> 
> mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
> This patch expands mstatus and vsstatus to uint64_t instead of
> target_ulong so that it can be saved as one unit and reduce some
> ifdefs in the code.
> 
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-id: 20201026115530.304-2-jiangyifei@huawei.com
> ---
>  target/riscv/cpu.h        | 24 +++++++++++-------------
>  target/riscv/cpu_bits.h   | 19 ++++---------------
>  target/riscv/cpu.c        |  8 +++++---
>  target/riscv/cpu_helper.c | 35 +++++++----------------------------
>  target/riscv/csr.c        | 18 ++++++++++--------
>  target/riscv/op_helper.c  | 11 ++++-------
>  6 files changed, 41 insertions(+), 74 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~



  parent reply	other threads:[~2020-11-03 20:20 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 19:50 [PATCH v3 0/7] Fix the Hypervisor access functions Alistair Francis
2020-11-03 19:50 ` [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 19:52   ` Alistair Francis
2020-11-03 20:19   ` Richard Henderson [this message]
2020-11-03 19:50 ` [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-11-03 20:20   ` Richard Henderson
2020-11-04  4:42     ` Alistair Francis
2020-11-03 19:51 ` [PATCH v3 3/7] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-11-03 19:51 ` [PATCH v3 4/7] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-11-03 19:51 ` [PATCH v3 5/7] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-11-03 19:51 ` [PATCH v3 6/7] target/riscv: Remove the Hypervisor access check function Alistair Francis
2020-11-03 20:26   ` Richard Henderson
2020-11-03 19:51 ` [PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
2020-11-03 20:27   ` Richard Henderson

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