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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-716bb22d45fsm7482622a12.86.2024.06.25.11.18.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jun 2024 11:18:31 -0700 (PDT) Message-ID: <2cb94b34-1a5f-4dc9-bec4-78c7008cd79d@linaro.org> Date: Tue, 25 Jun 2024 11:18:29 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events To: Alexei Filippov , palmer@dabbelt.com Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, liwei1518@gmail.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20240625144643.34733-1-alexei.filippov@syntacore.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240625144643.34733-1-alexei.filippov@syntacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::230 (deferred) Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/25/24 07:46, Alexei Filippov wrote: > Was added call backs for machine specific pmu events. > Simplify monitor functions by adding new hash table, which going to map > counter number and event index. > Was added read/write callbacks which going to simplify support for events, > which expected to have different behavior. > > Signed-off-by: Alexei Filippov > --- > Changes since v2: > -rebased to latest master > target/riscv/cpu.h | 9 +++ > target/riscv/csr.c | 43 +++++++++----- > target/riscv/pmu.c | 139 ++++++++++++++++++++++----------------------- > target/riscv/pmu.h | 11 ++-- > 4 files changed, 115 insertions(+), 87 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6fe0d712b4..fbf82b050b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -374,6 +374,13 @@ struct CPUArchState { > uint64_t (*rdtime_fn)(void *); > void *rdtime_fn_arg; > > + /*machine specific pmu callback */ > + void (*pmu_ctr_write)(PMUCTRState *counter, uint32_t event_idx, > + target_ulong val, bool high_half); > + target_ulong (*pmu_ctr_read)(PMUCTRState *counter, uint32_t event_idx, > + bool high_half); > + bool (*pmu_vendor_support)(uint32_t event_idx); Do these really belong in CPUArchState, rather than RISCVCPUClass? Surely there's more to this series, since these fields are never set... r~