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([2001:8003:3a49:fd00:91e3:5d6a:70ac:f94c]) by smtp.gmail.com with ESMTPSA id o9sm11870148pfw.86.2022.02.01.16.37.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Feb 2022 16:37:18 -0800 (PST) Message-ID: <2cb994f2-85e1-451f-c83c-a8403135cdc0@linaro.org> Date: Wed, 2 Feb 2022 11:37:10 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults Content-Language: en-US To: Alistair Francis References: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> <9fe41ac9-f0d9-1122-7ec3-3f20e3667826@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , "open list:RISC-V" , David Hildenbrand , Bin Meng , "qemu-devel@nongnu.org Developers" , Peter Xu , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Palmer Dabbelt , Alistair Francis , Paolo Bonzini , Bin Meng , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/1/22 15:40, Alistair Francis wrote: >> Alistair, you're only changing the reporting of MMIO faults for which read permission is >> missing. Importantly, the actual permission check is done elsewhere, and you aren't >> changing that to perform a write access check. Also, you very much need to handle normal > > I'm a little confused with this part. > > Looking at tcg_gen_atomic_cmpxchg_i64() for example we either: > 1. call tcg_gen_qemu_ld_i64() then tcg_gen_qemu_st_i64() > 2. call table_cmpxchg[] which eventually calls atomic_mmu_lookup() > 3. call tcg_gen_atomic_cmpxchg_i32() which is pretty much the same as > the above two > > That means in both cases we end up performing a load or tlb_fill(.., > MMU_DATA_LOAD, ..) operation as well as a store operation. Yep... > So we are already performing a write permission check... ... but we're doing so *after* the load. Which means that for a completely unmapped page (as opposed to a read-only page) we will generate a read fault, which generates RISCV_EXCP_LOAD_ACCESS_FAULT and *not* RISCV_EXCP_STORE_AMO_ACCESS_FAULT. So we need to check for write permission first, before performing the load. > Can't we just do the check in the slow path? By the time we get to the > fast path shouldn't we already have permissions? No, the fast path performs the permissions check on one bit [rwx] depending on which tlb comparator it loads. > As in add a new INDEX_op_qemu_ld_write_perm_i32/i64, make edits to > atomic_mmu_lookup() and all of the plumbing for those? That's one possibility, sure. r~