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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42f7d331a4fsm34341805f8f.33.2025.12.09.02.10.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Dec 2025 02:10:33 -0800 (PST) Message-ID: <2ce54748-5a35-4ae9-9dea-f893a3467825@redhat.com> Date: Tue, 9 Dec 2025 11:10:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 31/32] vfio: Synthesize vPASID capability to VM To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: eric.auger@redhat.com, peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, kjaju@nvidia.com References: <20251031105005.24618-1-skolothumtho@nvidia.com> <20251031105005.24618-32-skolothumtho@nvidia.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Autocrypt: addr=clg@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello Shameer, Yi, On 10/31/25 11:50, Shameer Kolothum wrote: > From: Yi Liu > > If user wants to expose PASID capability in vIOMMU, then VFIO would also > report the PASID cap for this device if the underlying hardware supports > it as well. > > As a start, this chooses to put the vPASID cap in the last 8 bytes of the > vconfig space. This is a choice in the good hope of no conflict with any > existing cap or hidden registers. For the devices that has hidden registers, > user should figure out a proper offset for the vPASID cap. This may require > an option for user to config it. Here we leave it as a future extension. > There are more discussions on the mechanism of finding the proper offset. > > https://lore.kernel.org/kvm/BN9PR11MB5276318969A212AD0649C7BE8CBE2@BN9PR11MB5276.namprd11.prod.outlook.com/ > > Since we add a check to ensure the vIOMMU supports PASID, only devices > under those vIOMMUs can synthesize the vPASID capability. This gives > users control over which devices expose vPASID. > > Signed-off-by: Yi Liu > Tested-by: Zhangfei Gao > Signed-off-by: Shameer Kolothum > --- > hw/vfio/pci.c | 37 +++++++++++++++++++++++++++++++++++++ > include/hw/iommu.h | 1 + > 2 files changed, 38 insertions(+) > > diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c > index 06b06afc2b..2054eac897 100644 > --- a/hw/vfio/pci.c > +++ b/hw/vfio/pci.c > @@ -24,6 +24,7 @@ > #include > > #include "hw/hw.h" > +#include "hw/iommu.h" > #include "hw/pci/msi.h" > #include "hw/pci/msix.h" > #include "hw/pci/pci_bridge.h" > @@ -2500,7 +2501,12 @@ static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev, uint16_t pos) > > static void vfio_add_ext_cap(VFIOPCIDevice *vdev) > { > + HostIOMMUDevice *hiod = vdev->vbasedev.hiod; > + HostIOMMUDeviceClass *hiodc = HOST_IOMMU_DEVICE_GET_CLASS(hiod); > PCIDevice *pdev = PCI_DEVICE(vdev); > + uint64_t max_pasid_log2 = 0; > + bool pasid_cap_added = false; > + uint64_t hw_caps; > uint32_t header; > uint16_t cap_id, next, size; > uint8_t cap_ver; > @@ -2578,12 +2584,43 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) > pcie_add_capability(pdev, cap_id, cap_ver, next, size); > } > break; > + case PCI_EXT_CAP_ID_PASID: > + pasid_cap_added = true; > + /* fallthrough */ > default: > pcie_add_capability(pdev, cap_id, cap_ver, next, size); > } > > } > > +#ifdef CONFIG_IOMMUFD The HostIOMMUDevice concept was introduced to abstract the use of the Host IOMMU backends in VFIO (and other parts of QEMU): - the VFIO IOMMU type1 backend, also referred as 'legacy', - IOMMUFD Adding code in VFIO under CONFIG_IOMMUFD should be avoided always when possible. There are exceptions, such as for the definition of the properties below in this file. This is, however, due to the dual-bus nature of the VFIO devices and the limitation of QEMU class inheritance. In this case, I think we can extend HostIOMMUDevice and associated class, to handle PASID support. Please rework this patch. I can merge as a prereq change. Also, IOMMUFD backend is not supported on all platforms, so these changes, even if correct, won't compile. Thanks, C. > + /* > + * Although we check for PCI_EXT_CAP_ID_PASID above, the Linux VFIO > + * framework currently hides this capability. Try to retrieve it > + * through alternative kernel interfaces (e.g. IOMMUFD APIs). > + */ > + if (!pasid_cap_added && hiodc->get_cap) { > + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_GENERIC_HW, &hw_caps, NULL); > + hiodc->get_cap(hiod, HOST_IOMMU_DEVICE_CAP_MAX_PASID_LOG2, > + &max_pasid_log2, NULL); > + } > + > + /* > + * If supported, adds the PASID capability in the end of the PCIe config > + * space. TODO: Add option for enabling pasid at a safe offset. > + */ > + if (max_pasid_log2 && (pci_device_get_viommu_flags(pdev) & > + VIOMMU_FLAG_PASID_SUPPORTED)) { > + bool exec_perm = (hw_caps & IOMMU_HW_CAP_PCI_PASID_EXEC) ? true : false; > + bool priv_mod = (hw_caps & IOMMU_HW_CAP_PCI_PASID_PRIV) ? true : false; > + > + pcie_pasid_init(pdev, PCIE_CONFIG_SPACE_SIZE - PCI_EXT_CAP_PASID_SIZEOF, > + max_pasid_log2, exec_perm, priv_mod); > + /* PASID capability is fully emulated by QEMU */ > + memset(vdev->emulated_config_bits + pdev->exp.pasid_cap, 0xff, 8); > + } > +#endif > + > /* Cleanup chain head ID if necessary */ > if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { > pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); > diff --git a/include/hw/iommu.h b/include/hw/iommu.h > index 9b8bb94fc2..9635770bee 100644 > --- a/include/hw/iommu.h > +++ b/include/hw/iommu.h > @@ -20,6 +20,7 @@ > enum viommu_flags { > /* vIOMMU needs nesting parent HWPT to create nested HWPT */ > VIOMMU_FLAG_WANT_NESTING_PARENT = BIT_ULL(0), > + VIOMMU_FLAG_PASID_SUPPORTED = BIT_ULL(1), > }; > > #endif /* HW_IOMMU_H */