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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id r5-20020a056808210500b003a020d24d7dsm1488213oiw.56.2023.06.30.09.51.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jun 2023 09:51:56 -0700 (PDT) Message-ID: <2d049db0-48ac-14a2-13f3-644e42cd0716@gmail.com> Date: Fri, 30 Jun 2023 13:51:54 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] pnv/psi: Allow access to PSI registers through xscom Content-Language: en-US To: Frederic Barrat , clg@kaod.org, joel@jms.id.au, qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20230630102609.193214-1-fbarrat@linux.ibm.com> From: Daniel Henrique Barboza In-Reply-To: <20230630102609.193214-1-fbarrat@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.095, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/30/23 07:26, Frederic Barrat wrote: > skiboot only uses mmio to access the PSI registers (once the BAR is > set) but we don't have any reason to block the accesses through > xscom. This patch enables xscom access to the PSI registers. It > converts the xscom addresses to mmio addresses, which requires a bit > of care for the PSIHB, then reuse the existing mmio ops. > > Signed-off-by: Frederic Barrat > --- Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel > hw/ppc/pnv_psi.c | 31 +++++++++++++++++++++---------- > 1 file changed, 21 insertions(+), 10 deletions(-) > > diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c > index 8aa09ab26b..46da58dff8 100644 > --- a/hw/ppc/pnv_psi.c > +++ b/hw/ppc/pnv_psi.c > @@ -121,8 +121,12 @@ > #define PSIHB9_BAR_MASK 0x00fffffffff00000ull > #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull > > +/* mmio address to xscom address */ > #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) > > +/* xscom address to mmio address */ > +#define PSIHB_MMIO(reg) ((reg - PSIHB_XSCOM_BAR) << 3) > + > static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) > { > PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); > @@ -769,24 +773,31 @@ static const MemoryRegionOps pnv_psi_p9_mmio_ops = { > > static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) > { > - /* No read are expected */ > - qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr); > - return -1; > + uint32_t reg = addr >> 3; > + uint64_t val = -1; > + > + if (reg < PSIHB_XSCOM_BAR) { > + /* FIR, not modeled */ > + qemu_log_mask(LOG_UNIMP, "PSI: xscom read at 0x%08x\n", reg); > + } else { > + val = pnv_psi_p9_mmio_read(opaque, PSIHB_MMIO(reg), size); > + } > + return val; > } > > static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, > uint64_t val, unsigned size) > { > PnvPsi *psi = PNV_PSI(opaque); > + uint32_t reg = addr >> 3; > > - /* XSCOM is only used to set the PSIHB MMIO region */ > - switch (addr >> 3) { > - case PSIHB_XSCOM_BAR: > + if (reg < PSIHB_XSCOM_BAR) { > + /* FIR, not modeled */ > + qemu_log_mask(LOG_UNIMP, "PSI: xscom write at 0x%08x\n", reg); > + } else if (reg == PSIHB_XSCOM_BAR) { > pnv_psi_set_bar(psi, val); > - break; > - default: > - qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n", > - addr); > + } else { > + pnv_psi_p9_mmio_write(opaque, PSIHB_MMIO(reg), val, size); > } > } >