From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions
Date: Mon, 11 Jan 2021 18:54:54 -1000 [thread overview]
Message-ID: <2d0f3c27-8f0d-1386-7ab0-9e6e5e1a6c53@linaro.org> (raw)
In-Reply-To: <20210112022001.20521-9-frank.chang@sifive.com>
On 1/11/21 4:19 PM, frank.chang@sifive.com wrote:
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shli_tl(t, t, a->shamt);
> -
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> + return gen_shifti(ctx, a, tcg_gen_shl_tl);
> } /* NOP otherwise */
> return true;
> }
>
> static bool trans_srli(DisasContext *ctx, arg_srli *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_shri_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> + return gen_shifti(ctx, a, tcg_gen_shr_tl);
> } /* NOP otherwise */
> return true;
> }
>
> static bool trans_srai(DisasContext *ctx, arg_srai *a)
> {
> - if (a->shamt >= TARGET_LONG_BITS) {
> - return false;
> - }
> -
> if (a->rd != 0) {
> - TCGv t = tcg_temp_new();
> - gen_get_gpr(t, a->rs1);
> -
> - tcg_gen_sari_tl(t, t, a->shamt);
> - gen_set_gpr(a->rd, t);
> - tcg_temp_free(t);
> + return gen_shifti(ctx, a, tcg_gen_sar_tl);
> } /* NOP otherwise */
> return true;
> }
This removes the illegal instruction check for rd == 0.
In general you don't need the rd != 0 check, because gen_set_gpr will handle it
(and it'll be exceedingly rare, and therefore not worth checking by hand).
r~
next prev parent reply other threads:[~2021-01-12 5:03 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 2:19 [RFC v3 00/16] support subsets of bitmanip extension frank.chang
2021-01-12 2:19 ` [RFC v3 01/16] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-01-12 2:19 ` [RFC v3 02/16] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-01-12 2:19 ` [RFC v3 03/16] target/riscv: rvb: count bits set frank.chang
2021-01-12 2:19 ` [RFC v3 04/16] target/riscv: rvb: logic-with-negate frank.chang
2021-01-12 5:46 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 05/16] target/riscv: rvb: pack two words into one register frank.chang
2021-01-12 2:19 ` [RFC v3 06/16] target/riscv: rvb: min/max instructions frank.chang
2021-01-12 2:19 ` [RFC v3 07/16] target/riscv: rvb: sign-extend instructions frank.chang
2021-01-12 2:19 ` [RFC v3 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-01-12 4:54 ` Richard Henderson [this message]
2021-01-12 5:27 ` Frank Chang
2021-01-12 2:19 ` [RFC v3 09/16] target/riscv: rvb: single-bit instructions frank.chang
2021-01-12 4:56 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 10/16] target/riscv: rvb: shift ones frank.chang
2021-01-12 2:19 ` [RFC v3 11/16] target/riscv: rvb: rotate (left/right) frank.chang
2021-01-12 5:45 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 12/16] target/riscv: rvb: generalized reverse frank.chang
2021-01-12 2:19 ` [RFC v3 13/16] target/riscv: rvb: generalized or-combine frank.chang
2021-01-12 5:47 ` Richard Henderson
2021-01-12 2:19 ` [RFC v3 14/16] target/riscv: rvb: address calculation frank.chang
2021-01-12 2:19 ` [RFC v3 15/16] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-01-12 2:19 ` [RFC v3 16/16] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-01-12 5:47 ` Richard Henderson
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