From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aynZt-0006Xa-0j for qemu-devel@nongnu.org; Fri, 06 May 2016 17:46:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aynZh-0003Co-Ep for qemu-devel@nongnu.org; Fri, 06 May 2016 17:46:23 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34880) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aynZg-00038E-7m for qemu-devel@nongnu.org; Fri, 06 May 2016 17:46:17 -0400 Received: by mail-qk0-x243.google.com with SMTP id z3so7147332qkb.2 for ; Fri, 06 May 2016 14:46:02 -0700 (PDT) Sender: Richard Henderson References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> <1462396135-20925-1-git-send-email-laurent@vivier.eu> <1462396135-20925-7-git-send-email-laurent@vivier.eu> From: Richard Henderson Message-ID: <2d48214f-f757-7144-6ca7-c0ed6c3ca94d@twiddle.net> Date: Fri, 6 May 2016 11:45:53 -1000 MIME-Version: 1.0 In-Reply-To: <1462396135-20925-7-git-send-email-laurent@vivier.eu> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 39/52] target-m68k: movem List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Vivier , qemu-devel@nongnu.org Cc: schwab@linux-m68k.org, gerg@uclinux.org, agraf@suse.de A more verbose commit message is required here. On 05/04/2016 11:08 AM, Laurent Vivier wrote: > @@ -1724,21 +1726,40 @@ DISAS_INSN(movem) > addr = tcg_temp_new(); > tcg_gen_mov_i32(addr, tmp); > is_load = ((insn & 0x0400) != 0); > - for (i = 0; i < 16; i++, mask >>= 1) { > - if (mask & 1) { > - if (i < 8) > - reg = DREG(i, 0); > - else > - reg = AREG(i, 0); > - if (is_load) { > - tmp = gen_load(s, OS_LONG, addr, 0); > - tcg_gen_mov_i32(reg, tmp); > - } else { > - gen_store(s, OS_LONG, addr, reg); > - } > - if (mask != 1) > - tcg_gen_addi_i32(addr, addr, 4); > - } > + opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; > + incr = opsize_bytes(opsize); > + if (!is_load && (insn & 070) == 040) { > + for (i = 15; i >= 0; i--, mask >>= 1) { > + if (mask & 1) { > + if (i < 8) > + reg = DREG(i, 0); > + else > + reg = AREG(i, 0); > + gen_store(s, opsize, addr, reg); > + if (mask != 1) > + tcg_gen_subi_i32(addr, addr, incr); > + } > + } > + tcg_gen_mov_i32(AREG(insn, 0), addr); Missing this bit from the manual: For the MC68020, MC68030, MC68040, and CPU32, if the addressing register is also moved to memory, the value written is the initial register value decremented by the size of the operation. The MC68000 and MC68010 write the initial register value (not decremented). You appear to be implementing only the latter. > + } else { > + for (i = 0; i < 16; i++, mask >>= 1) { > + if (mask & 1) { > + if (i < 8) > + reg = DREG(i, 0); > + else > + reg = AREG(i, 0); > + if (is_load) { > + tmp = gen_load(s, opsize, addr, 1); > + tcg_gen_mov_i32(reg, tmp); > + } else { > + gen_store(s, opsize, addr, reg); > + } > + if (mask != 1 || (insn & 070) == 030) > + tcg_gen_addi_i32(addr, addr, incr); > + } > + } For loads, we surely should be doing something more in order to properly emulate the access trap that might occur here. I seem to recall saving the effective address, a CM bit in the exception stack frame, and RTE restarting the movem with the saved effective address. r~