Re: [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model

[Miles Glenn <milesg@linux.ibm.com>]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> The PNV LPC model needs snapshot/migration support.  Added a VMSTATE
> descriptor to save model data and an associated post_load() method.
> 
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
>  hw/ppc/pnv_lpc.c | 39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index f6beba0917..7f11fd312a 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -30,6 +30,7 @@
>  #include "hw/ppc/pnv_lpc.h"
>  #include "hw/ppc/pnv_xscom.h"
>  #include "hw/ppc/fdt.h"
> +#include "migration/vmstate.h"
>  
>  #include <libfdt.h>
>  
> @@ -777,11 +778,49 @@ static const TypeInfo pnv_lpc_power9_info = {
>      .class_init    = pnv_lpc_power9_class_init,
>  };
>  
> +static int vmstate_pnv_lpc_post_load(void *opaque, int version_id)
> +{
> +    PnvLpcController *lpc = PNV_LPC(opaque);
> +
> +    memory_region_set_alias_offset(&lpc->opb_isa_fw,
> +                                   lpc->lpc_hc_fw_seg_idsel * LPC_FW_OPB_SIZE);
> +    pnv_lpc_eval_serirq_routes(lpc);
> +
> +    pnv_lpc_eval_irqs(lpc);
> +    return 0;
> +}
> +
> +static const VMStateDescription vmstate_pnv_lpc = {
> +    .name = TYPE_PNV_LPC,
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .post_load = vmstate_pnv_lpc_post_load,
> +    .fields = (const VMStateField[]) {
> +        VMSTATE_UINT64(eccb_stat_reg,       PnvLpcController),
> +        VMSTATE_UINT32(eccb_data_reg,       PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_route0,      PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_route1,      PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_stat,        PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_mask,        PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_pol,         PnvLpcController),
> +        VMSTATE_UINT32(opb_irq_input,       PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_irq_inputs,   PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_fw_seg_idsel, PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_irqser_ctrl,  PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_irqmask,      PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_irqstat,      PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_error_addr,   PnvLpcController),
> +        VMSTATE_UINT32(lpc_hc_fw_rd_acc_size,     PnvLpcController),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
>  static void pnv_lpc_power10_class_init(ObjectClass *klass, const void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
>  
>      dc->desc = "PowerNV LPC Controller POWER10";
> +    dc->vmsd = &vmstate_pnv_lpc;
>  }
>  
>  static const TypeInfo pnv_lpc_power10_info = {