From: "Cédric Le Goater" <clg@kaod.org>
To: Jamin Lin <jamin_lin@aspeedtech.com>,
Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com
Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
Date: Wed, 29 Jan 2025 18:03:50 +0100 [thread overview]
Message-ID: <2d9247ab-34dd-4dde-a9c0-c04c2d8a1a18@kaod.org> (raw)
In-Reply-To: <20250121070424.2465942-2-jamin_lin@aspeedtech.com>
On 1/21/25 08:04, Jamin Lin wrote:
> The design of the INTC has significant changes in the AST2700 A1. In the
> AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
> there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
>
> The previous INTC model only supported the AST2700 A0 and was implemented for
> the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model, rename INTC
> to INTC0.
Why not introduce definitions with _INTC_IO_ and leave alone the current
instead ? Do we expect to have more than 2 INTC controllers ?
Thanks,
C.
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 6 +--
> hw/intc/aspeed_intc.c | 90 +++++++++++++++++------------------
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/intc/aspeed_intc.h | 2 +-
> 4 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4114e15ddd..ba461fcd3c 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ETH2] = 0x14060000,
> [ASPEED_DEV_ETH3] = 0x14070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> - [ASPEED_DEV_INTC] = 0x12100000,
> + [ASPEED_DEV_INTC0] = 0x12100000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_SLIIO] = 0x14C1E000,
> [ASPEED_GIC_DIST] = 0x12200000,
> @@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
> object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
> - object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
> + object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC0);
>
> snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
> object_initialize_child(obj, "adc", &s->adc, typename);
> @@ -517,7 +517,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> }
>
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
> - sc->memmap[ASPEED_DEV_INTC]);
> + sc->memmap[ASPEED_DEV_INTC0]);
>
> /* GICINT orgates -> INTC -> GIC */
> for (i = 0; i < ic->num_ints; i++) {
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 126b711b94..df4da759e1 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -14,27 +14,27 @@
> #include "hw/registerfields.h"
> #include "qapi/error.h"
>
> -/* INTC Registers */
> -REG32(GICINT128_EN, 0x1000)
> -REG32(GICINT128_STATUS, 0x1004)
> -REG32(GICINT129_EN, 0x1100)
> -REG32(GICINT129_STATUS, 0x1104)
> -REG32(GICINT130_EN, 0x1200)
> -REG32(GICINT130_STATUS, 0x1204)
> -REG32(GICINT131_EN, 0x1300)
> -REG32(GICINT131_STATUS, 0x1304)
> -REG32(GICINT132_EN, 0x1400)
> -REG32(GICINT132_STATUS, 0x1404)
> -REG32(GICINT133_EN, 0x1500)
> -REG32(GICINT133_STATUS, 0x1504)
> -REG32(GICINT134_EN, 0x1600)
> -REG32(GICINT134_STATUS, 0x1604)
> -REG32(GICINT135_EN, 0x1700)
> -REG32(GICINT135_STATUS, 0x1704)
> -REG32(GICINT136_EN, 0x1800)
> -REG32(GICINT136_STATUS, 0x1804)
> -
> -#define GICINT_STATUS_BASE R_GICINT128_STATUS
> +/* AST2700 INTC0 Registers */
> +REG32(INTC0_GICINT128_EN, 0x1000)
> +REG32(INTC0_GICINT128_STATUS, 0x1004)
> +REG32(INTC0_GICINT129_EN, 0x1100)
> +REG32(INTC0_GICINT129_STATUS, 0x1104)
> +REG32(INTC0_GICINT130_EN, 0x1200)
> +REG32(INTC0_GICINT130_STATUS, 0x1204)
> +REG32(INTC0_GICINT131_EN, 0x1300)
> +REG32(INTC0_GICINT131_STATUS, 0x1304)
> +REG32(INTC0_GICINT132_EN, 0x1400)
> +REG32(INTC0_GICINT132_STATUS, 0x1404)
> +REG32(INTC0_GICINT133_EN, 0x1500)
> +REG32(INTC0_GICINT133_STATUS, 0x1504)
> +REG32(INTC0_GICINT134_EN, 0x1600)
> +REG32(INTC0_GICINT134_STATUS, 0x1604)
> +REG32(INTC0_GICINT135_EN, 0x1700)
> +REG32(INTC0_GICINT135_STATUS, 0x1704)
> +REG32(INTC0_GICINT136_EN, 0x1800)
> +REG32(INTC0_GICINT136_STATUS, 0x1804)
> +
> +#define GICINT_STATUS_BASE R_INTC0_GICINT128_STATUS
>
> static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
> {
> @@ -153,15 +153,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
> trace_aspeed_intc_write(offset, size, data);
>
> switch (addr) {
> - case R_GICINT128_EN:
> - case R_GICINT129_EN:
> - case R_GICINT130_EN:
> - case R_GICINT131_EN:
> - case R_GICINT132_EN:
> - case R_GICINT133_EN:
> - case R_GICINT134_EN:
> - case R_GICINT135_EN:
> - case R_GICINT136_EN:
> + case R_INTC0_GICINT128_EN:
> + case R_INTC0_GICINT129_EN:
> + case R_INTC0_GICINT130_EN:
> + case R_INTC0_GICINT131_EN:
> + case R_INTC0_GICINT132_EN:
> + case R_INTC0_GICINT133_EN:
> + case R_INTC0_GICINT134_EN:
> + case R_INTC0_GICINT135_EN:
> + case R_INTC0_GICINT136_EN:
> irq = (offset & 0x0f00) >> 8;
>
> if (irq >= aic->num_ints) {
> @@ -202,15 +202,15 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
> }
> s->regs[addr] = data;
> break;
> - case R_GICINT128_STATUS:
> - case R_GICINT129_STATUS:
> - case R_GICINT130_STATUS:
> - case R_GICINT131_STATUS:
> - case R_GICINT132_STATUS:
> - case R_GICINT133_STATUS:
> - case R_GICINT134_STATUS:
> - case R_GICINT135_STATUS:
> - case R_GICINT136_STATUS:
> + case R_INTC0_GICINT128_STATUS:
> + case R_INTC0_GICINT129_STATUS:
> + case R_INTC0_GICINT130_STATUS:
> + case R_INTC0_GICINT131_STATUS:
> + case R_INTC0_GICINT132_STATUS:
> + case R_INTC0_GICINT133_STATUS:
> + case R_INTC0_GICINT134_STATUS:
> + case R_INTC0_GICINT135_STATUS:
> + case R_INTC0_GICINT136_STATUS:
> irq = (offset & 0x0f00) >> 8;
>
> if (irq >= aic->num_ints) {
> @@ -336,26 +336,26 @@ static const TypeInfo aspeed_intc_info = {
> .abstract = true,
> };
>
> -static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
> +static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
>
> - dc->desc = "ASPEED 2700 INTC Controller";
> + dc->desc = "ASPEED 2700 INTC 0 Controller";
> aic->num_lines = 32;
> aic->num_ints = 9;
> }
>
> -static const TypeInfo aspeed_2700_intc_info = {
> - .name = TYPE_ASPEED_2700_INTC,
> +static const TypeInfo aspeed_2700_intc0_info = {
> + .name = TYPE_ASPEED_2700_INTC0,
> .parent = TYPE_ASPEED_INTC,
> - .class_init = aspeed_2700_intc_class_init,
> + .class_init = aspeed_2700_intc0_class_init,
> };
>
> static void aspeed_intc_register_types(void)
> {
> type_register_static(&aspeed_intc_info);
> - type_register_static(&aspeed_2700_intc_info);
> + type_register_static(&aspeed_2700_intc0_info);
> }
>
> type_init(aspeed_intc_register_types);
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 689f52dae8..51e585e3e4 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -194,7 +194,7 @@ enum {
> ASPEED_DEV_EHCI1,
> ASPEED_DEV_EHCI2,
> ASPEED_DEV_VIC,
> - ASPEED_DEV_INTC,
> + ASPEED_DEV_INTC0,
> ASPEED_DEV_SDMC,
> ASPEED_DEV_SCU,
> ASPEED_DEV_ADC,
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 18cb43476c..10718ed4a1 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -13,7 +13,7 @@
> #include "hw/or-irq.h"
>
> #define TYPE_ASPEED_INTC "aspeed.intc"
> -#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> +#define TYPE_ASPEED_2700_INTC0 TYPE_ASPEED_INTC "0" "-ast2700"
> OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>
> #define ASPEED_INTC_NR_REGS (0x2000 >> 2)
next prev parent reply other threads:[~2025-01-29 17:05 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater [this message]
2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery
2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
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