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([2602:ae:1549:801:30c1:2484:a853:233d]) by smtp.gmail.com with ESMTPSA id k12-20020a170902ce0c00b0016c46ff9741sm9309332plg.67.2022.07.25.07.46.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Jul 2022 07:46:03 -0700 (PDT) Message-ID: <2d957926-ef9c-eae5-d78f-3acc04d047cb@linaro.org> Date: Mon, 25 Jul 2022 07:46:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v7 01/92] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Content-Language: en-US To: Zenghui Yu Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , andrew.jones@linux.dev References: <20210525010358.152808-1-richard.henderson@linaro.org> <20210525010358.152808-2-richard.henderson@linaro.org> <8e2ac59a-af4d-0f2c-455b-b9ed07b1e56a@huawei.com> From: Richard Henderson In-Reply-To: <8e2ac59a-af4d-0f2c-455b-b9ed07b1e56a@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/25/22 00:05, Zenghui Yu wrote: >> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c >> index dff85f6db9..37ceadd9a9 100644 >> --- a/target/arm/kvm64.c >> +++ b/target/arm/kvm64.c >> @@ -647,17 +647,26 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) >> >>      sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; >> >> -    kvm_arm_destroy_scratch_host_vcpu(fdarray); >> - >> -    if (err < 0) { >> -        return false; >> -    } >> - >>      /* Add feature bits that can't appear until after VCPU init. */ >>      if (sve_supported) { >>          t = ahcf->isar.id_aa64pfr0; >>          t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); >>          ahcf->isar.id_aa64pfr0 = t; >> + >> +        /* >> +         * Before v5.1, KVM did not support SVE and did not expose >> +         * ID_AA64ZFR0_EL1 even as RAZ.  After v5.1, KVM still does >> +         * not expose the register to "user" requests like this >> +         * unless the host supports SVE. >> +         */ >> +        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, >> +                              ARM64_SYS_REG(3, 0, 0, 4, 4)); > > If I read it correctly, we haven't yet enabled SVE for the scratch vcpu > (using the KVM_ARM_VCPU_INIT ioctl with KVM_ARM_VCPU_SVE). KVM will > therefore expose ID_AA64ZFR0_EL1 to userspace as RAZ at this point and > isar.id_aa64zfr0 is reset to 0. I wonder if it was intentional? You are correct, this is a bug. It appears this is hidden because nothing else actually depends on the value within the context of --accel=kvm, e.g. migration. r~