From: Richard Henderson <richard.henderson@linaro.org>
To: Joel Sing <joel@sing.id.au>
Cc: me@carlosedp.com, qemu-riscv@nongnu.org, palmer@sifive.com,
qemu-devel@nongnu.org, Alistair.Francis@wdc.com,
marco@decred.org
Subject: Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Date: Tue, 25 Jun 2019 17:36:28 +0200 [thread overview]
Message-ID: <2dec03cb-22af-4d0d-f182-3bee9db83d6f@linaro.org> (raw)
In-Reply-To: <20190624180837.GM61734@hippo.sing.id.au>
On 6/24/19 8:08 PM, Joel Sing wrote:
> Regarding the alignment for reservations, the
> specification does require this, although I do not recall seeing any enforcement
> of this by qemu itself.
Ah, I see it now. Enforcement begins here:
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
REQUIRE_EXT(ctx, RVA);
return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
^^^^^^^^
This will force softmmu (but notably not linux-user; a design limitation) to
generate an alignment fault for an unaligned address.
r~
next prev parent reply other threads:[~2019-06-25 15:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-16 19:19 [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64 Joel Sing
2019-06-16 20:54 ` no-reply
2019-06-17 23:52 ` Richard Henderson
2019-06-24 6:42 ` Palmer Dabbelt
2019-06-24 18:08 ` Joel Sing
2019-06-25 15:36 ` Richard Henderson [this message]
2019-06-26 6:07 ` Palmer Dabbelt
2019-06-26 7:48 ` Richard Henderson
2019-06-26 8:25 ` Palmer Dabbelt
2019-06-26 8:30 ` Richard Henderson
2019-06-26 8:31 ` Palmer Dabbelt
2019-06-25 15:39 ` Richard Henderson
2019-06-26 6:07 ` Palmer Dabbelt
2019-09-24 18:29 ` Alistair Francis
2019-09-24 20:04 ` Palmer Dabbelt
2019-09-24 23:35 ` Alistair Francis
2019-09-25 1:01 ` Alistair Francis
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