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[178.202.40.247]) by smtp.gmail.com with ESMTPSA id az40-20020a05600c602800b0040ead8c6c0fsm3743588wmb.21.2024.01.22.05.22.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Jan 2024 05:22:09 -0800 (PST) Message-ID: <2dfd12d7-d3dc-47af-ba1c-2d2e25cb9c5f@canonical.com> Date: Mon, 22 Jan 2024 14:22:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] target/riscv: SMBIOS support for RISC-V virt machine Content-Language: en-US To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Paolo Bonzini , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <20231229120724.41383-1-heinrich.schuchardt@canonical.com> <20231229120724.41383-4-heinrich.schuchardt@canonical.com> <20240122-4f4cbce3692cd684e0409f9e@orel> <22105210-d8d1-4808-b9ed-41eee71c53ca@canonical.com> <20240122-195c4a8d0ece609441068e16@orel> From: Heinrich Schuchardt In-Reply-To: <20240122-195c4a8d0ece609441068e16@orel> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=185.125.188.123; envelope-from=heinrich.schuchardt@canonical.com; helo=smtp-relay-internal-1.canonical.com X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.289, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 22.01.24 13:59, Andrew Jones wrote: > On Mon, Jan 22, 2024 at 01:28:18PM +0100, Heinrich Schuchardt wrote: >> On 22.01.24 10:57, Andrew Jones wrote: >>> On Fri, Dec 29, 2023 at 01:07:23PM +0100, Heinrich Schuchardt wrote: > ... >>>> +#if defined(TARGET_RISCV32) >>>> + smbios_set_default_processor_family(0x200); >>>> +#elif defined(TARGET_RISCV64) >>>> + smbios_set_default_processor_family(0x201); >>>> +#endif >>> >>> I think we should use misa_mxl_max to determine the family, rather than >>> TARGET_*, because, iirc, we're slowly working our ways towards allowing >>> rv32 cpus to be instantiated with qemu-system-riscv64. >> >> Hello Andrew, >> >> thank you for reviewing. I guess you mean something like: >> >> if (riscv_is_32bit(&s->soc[0])) { >> smbios_set_default_processor_family(0x200); >> #if defined(TARGET_RISCV64) >> } else { >> smbios_set_default_processor_family(0x201); >> #endif >> } > > Yes, but I'm not sure we need the #ifdef around the 64-bit part. I just followed the style in riscv_cpu_validate_misa_mxl(). Best regards Heinrich > >> >> riscv_is_32bit returns harts->harts[0].env.misa_mxl_max == MXL_RV32. >> >> Some real hardware has a 32bit hart and multiple 64bit harts. Will QEMU >> support mixing harts with different bitness on the virt machine in future? >> In that case we would have to revisit the code using misa_mxl_max in >> multiple places. >> > > Never say never, but I don't think there has been much effort to support > these types of configurations with a single QEMU binary. My googling is > failing me right now, but I seem to recall that there may have been > efforts to implement Arm big.LITTLE with multiprocess QEMU [1]. IOW, I > think we're safe to use misa_mxl_max, since we'll have one for each QEMU > instance and we'll use a different QEMU instance for each hart bitness. > > [1] docs/system/multi-process.rst > > Thanks, > drew