From: Richard Henderson <richard.henderson@linaro.org>
To: matheus.ferst@eldorado.org.br, qemu-devel@nongnu.org,
qemu-ppc@nongnu.org
Cc: peter.maydell@linaro.org, danielhb413@gmail.com, groug@kaod.org,
f4bug@amsat.org, clg@kaod.org, alex.bennee@linaro.org,
aurelien@aurel32.net, david@gibson.dropbear.id.au
Subject: Re: [PATCH] tests/tcg/ppc64le: remove INT128 requirement to run non_signalling_xscv
Date: Fri, 17 Dec 2021 15:54:31 -0800 [thread overview]
Message-ID: <2e386a1a-17cd-1c04-4eab-480ecbae059f@linaro.org> (raw)
In-Reply-To: <20211216140951.1183987-1-matheus.ferst@eldorado.org.br>
On 12/16/21 6:09 AM, matheus.ferst@eldorado.org.br wrote:
> + asm("mtvsrd 0, %3\n\t" \
> + "xxswapd 0, 0\n\t" \
> + "mtvsrd 0, %2\n\t" \
This doesn't work. The lower half of vs0 is undefined after mtvsrd.
You actually want mtvsrdd 0, %2, %3, with "b" as the constraint for bh.
> + "mfvsrd %0, 0\n\t" \
> + "xxswapd 0, 0\n\t" \
> + "mfvsrd %1, 0\n\t" \
Drop the xxswapd and use mfvsrld.
Otherwise it looks ok.
r~
next prev parent reply other threads:[~2021-12-17 23:55 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 14:09 [PATCH] tests/tcg/ppc64le: remove INT128 requirement to run non_signalling_xscv matheus.ferst
2021-12-17 23:54 ` Richard Henderson [this message]
2021-12-20 12:18 ` Matheus K. Ferst
2021-12-20 19:18 ` Richard Henderson
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