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([2001:8003:c020:6900:324d:cbc2:5f8b:3a9d]) by smtp.gmail.com with ESMTPSA id d5-20020a170902cec500b001d07ebef623sm14444351plg.69.2023.12.28.15.46.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Dec 2023 15:46:15 -0800 (PST) Message-ID: <2e68509d-755c-473a-9d52-8ec5f947cc71@linaro.org> Date: Fri, 29 Dec 2023 10:46:09 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking Content-Language: en-US To: Alexey Baturo Cc: zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20231224044812.2072140-1-me@deliversmonkey.space> <20231224044812.2072140-6-me@deliversmonkey.space> From: Richard Henderson In-Reply-To: <20231224044812.2072140-6-me@deliversmonkey.space> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/24/23 15:48, Alexey Baturo wrote: > From: Alexey Baturo > > Signed-off-by: Alexey Baturo > --- > target/riscv/translate.c | 23 +++++++++++++++++++++-- > target/riscv/vector_helper.c | 10 ++++++++++ > 2 files changed, 31 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 1eb501e0d3..c0c5030e05 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -575,11 +575,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > /* Compute a canonical address from a register plus offset. */ > static TCGv get_address(DisasContext *ctx, int rs1, int imm) > { > + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); > TCGv addr = tcg_temp_new(); > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); > > tcg_gen_addi_tl(addr, src1, imm); > - if (get_address_xl(ctx) == MXL_RV32) { > + if (ctx->pm_pmm) { > + tcg_gen_shli_tl(addr, addr, pmlen); > + /* sign extend address by first non-masked bit otherwise zero extend */ > + if (ctx->pm_signext) { > + tcg_gen_sari_tl(addr, addr, pmlen); > + } else { > + tcg_gen_shri_tl(addr, addr, pmlen); > + } > + } else if (get_address_xl(ctx) == MXL_RV32) { > tcg_gen_ext32u_tl(addr, addr); > } > > @@ -589,11 +598,21 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) > /* Compute a canonical address from a register plus reg offset. */ > static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) > { > + int pmlen = riscv_pm_get_pmlen(ctx->pm_pmm); > TCGv addr = tcg_temp_new(); > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); > > tcg_gen_add_tl(addr, src1, offs); > - if (get_xl(ctx) == MXL_RV32) { > + /* sign extend address by first non-masked bit */ > + if (ctx->pm_pmm) { > + tcg_gen_shli_tl(addr, addr, pmlen); > + /* sign extend address by first non-masked bit otherwise zero extend */ > + if (ctx->pm_signext) { > + tcg_gen_sari_tl(addr, addr, pmlen); > + } else { > + tcg_gen_shri_tl(addr, addr, pmlen); > + } > + } else if (get_xl(ctx) == MXL_RV32) { > tcg_gen_ext32u_tl(addr, addr); Use tcg_gen_{s}extract_tl instead of two shifts. Also, it looks like it would be worth doing all of this once in riscv_tr_init_disas_context: if (get_xl(ctx) == MXL_RV32) { ctx->addr_width = 32; ctx->addr_signed = false; } else { pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm); ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); } then here in get_address_indexed if (ctx->addr_signed) { tcg_gen_sextract_tl(addr, addr, ctx->addr_width); } else { tcg_gen_extract_tl(addr, addr, ctx->addr_width); } > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 8e7a8e80a0..faa8f5820d 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -94,6 +94,16 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) > > static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) > { > + RISCVPmPmm pmm = riscv_pm_get_pmm(env); > + int pmlen = riscv_pm_get_pmlen(pmm); > + bool signext = !riscv_cpu_bare_mode(env); > + addr = addr << pmlen; > + /* sign/zero extend masked address by N-1 bit */ > + if (signext) { > + addr = (target_long)addr >> pmlen; > + } else { > + addr = addr >> pmlen; > + } > return addr; > } I think you could usefully exit early when likely(pmm == PMM_FIELD_DISABLED), avoiding the other computation. r~