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Wed, 14 Aug 2024 02:01:39 -0700 (PDT) Message-ID: <2ecd1ccc-ce2b-4432-a2a1-9af2dc70f037@linaro.org> Date: Wed, 14 Aug 2024 19:01:30 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 06/15] tcg/riscv: Implement vector load/store To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240813113436.831-1-zhiwei_liu@linux.alibaba.com> <20240813113436.831-7-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240813113436.831-7-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/13/24 21:34, LIU Zhiwei wrote: > @@ -827,14 +850,59 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, > static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, > TCGReg arg1, intptr_t arg2) > { > - RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD; > + RISCVInsn insn; > + > + if (type < TCG_TYPE_V64) { > + insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD; > + } else { > + tcg_debug_assert(arg >= TCG_REG_V1); > + switch (prev_vece) { > + case MO_8: > + insn = OPC_VLE8_V; > + break; > + case MO_16: > + insn = OPC_VLE16_V; > + break; > + case MO_32: > + insn = OPC_VLE32_V; > + break; > + case MO_64: > + insn = OPC_VLE64_V; > + break; > + default: > + g_assert_not_reached(); > + } > + } > tcg_out_ldst(s, insn, arg, arg1, arg2); tcg_out_ld/st are called directly from register allocation spill/fill. You'll need to set vtype here, and cannot rely on this having been done in tcg_out_vec_op. That said, with a little-endian host, the selected element size doesn't matter *too* much. A write of 8 uint16_t or a write of 2 uint64_t produces the same bits in memory. Therefore you can examine prev_vtype and adjust only if the vector length changes. But we do that -- e.g. load V256, store V256, store V128 to perform a 384-bit store for AArch64 SVE when VQ=3. Is there an advantage to using the vector load/store whole register insns, if the requested length is not too small? IIRC the NF field can be used to store multiples, but we can't store half of a register with these. r~