* [PULL 014/102] docs/system/ppc/powernv.rst: document KVM support status
2021-12-15 17:02 ` Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 015/102] ppc/pnv.c: fix "system-id" FDT when -uuid is set Cédric Le Goater
` (87 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211130133153.444601-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/ppc/powernv.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index edd45d1eaadd..c8f9762342d6 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -54,6 +54,19 @@ Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the
QEMU includes a prebuilt image of ``skiboot`` which is updated when a
more recent version is required by the models.
+Current acceleration status
+---------------------------
+
+KVM acceleration in Linux Power hosts is provided by the kvm-hv and
+kvm-pr modules. kvm-hv is adherent to PAPR and it's not compliant with
+powernv. kvm-pr in theory could be used as a valid accel option but
+this isn't supported by kvm-pr at this moment.
+
+To spare users from dealing with not so informative errors when attempting
+to use accel=kvm, the powernv machine will throw an error informing that
+KVM is not supported. This can be revisited in the future if kvm-pr (or
+any other KVM alternative) is usable as KVM accel for this machine.
+
Boot options
------------
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 015/102] ppc/pnv.c: fix "system-id" FDT when -uuid is set
2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 014/102] docs/system/ppc/powernv.rst: document KVM support status Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 016/102] docs: Introducing pseries documentation Cédric Le Goater
` (86 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid 7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt, "system-id", buf)): FDT_ERR_BADSTATE
This happens because we're using fdt_property_string(), which is a
sequential write function that is supposed to be used when we're
building a new FDT, in a case where read/writing into an existing FDT.
Fix it by using fdt_setprop_string() instead.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211207094858.744386-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e5b87e873095..44ae41a9cb6b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -522,7 +522,7 @@ static void *pnv_dt_create(MachineState *machine)
buf = qemu_uuid_unparse_strdup(&qemu_uuid);
_FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
if (qemu_uuid_set) {
- _FDT((fdt_property_string(fdt, "system-id", buf)));
+ _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
}
g_free(buf);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 016/102] docs: Introducing pseries documentation.
2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 014/102] docs/system/ppc/powernv.rst: document KVM support status Cédric Le Goater
2021-12-15 17:02 ` [PULL 015/102] ppc/pnv.c: fix "system-id" FDT when -uuid is set Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 017/102] docs: rSTify ppc-spapr-hcalls.txt Cédric Le Goater
` (85 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Leonardo Garcia, Peter Maydell, Richard Henderson,
Cédric Le Goater, David Gibson
From: Leonardo Garcia <lagarcia@br.ibm.com>
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
to this documentation, so that we only need to keep it updated in one
place.
0. https://wiki.qemu.org/Documentation/Platforms/POWER
1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/ppc/pseries.rst | 226 ++++++++++++++++++++++++++++++++++++
1 file changed, 226 insertions(+)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index 932d4dd17d29..e46f09d4c8d7 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -1,12 +1,238 @@
pSeries family boards (``pseries``)
===================================
+The Power machine para-virtualized environment described by the `Linux on Power
+Architecture Reference document (LoPAR)
+<https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_
+is called pSeries. This environment is also known as sPAPR, System p guests, or
+simply Power Linux guests (although it is capable of running other operating
+systems, such as AIX).
+
+Even though pSeries is designed to behave as a guest environment, it is also
+capable of acting as a hypervisor OS, providing, on that role, nested
+virtualization capabilities.
+
Supported devices
-----------------
+ * Multi processor support for many Power processors generations: POWER7,
+ POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
+ but its state is unknown.
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
+ * vPHB PCIe Host bridge.
+ * vscsi and vnet devices, compatible with the same devices available on a
+ PowerVM hypervisor with VIOS managing LPARs.
+ * Virtio based devices.
+ * PCIe device pass through.
+
Missing devices
---------------
+ * SPICE support.
Firmware
--------
+
+`SLOF <https://github.com/aik/SLOF>`_ (Slimline Open Firmware) is an
+implementation of the `IEEE 1275-1994, Standard for Boot (Initialization
+Configuration) Firmware: Core Requirements and Practices
+<https://standards.ieee.org/standard/1275-1994.html>`_.
+
+QEMU includes a prebuilt image of SLOF which is updated when a more recent
+version is required.
+
+Build directions
+----------------
+
+.. code-block:: bash
+
+ ./configure --target-list=ppc64-softmmu && make
+
+Running instructions
+--------------------
+
+Someone can select the pSeries machine type by running QEMU with the following
+options:
+
+.. code-block:: bash
+
+ qemu-system-ppc64 -M pseries <other QEMU arguments>
+
+sPAPR devices
+-------------
+
+The sPAPR specification defines a set of para-virtualized devices, which are
+also supported by the pSeries machine in QEMU and can be instantiated with the
+``-device`` option:
+
+* ``spapr-vlan`` : a virtual network interface.
+* ``spapr-vscsi`` : a virtual SCSI disk interface.
+* ``spapr-rng`` : a pseudo-device for passing random number generator data to the
+ guest (see the `H_RANDOM hypercall feature
+ <https://wiki.qemu.org/Features/HRandomHypercall>`_ for details).
+* ``spapr-vty``: a virtual teletype.
+* ``spapr-pci-host-bridge``: a PCI host bridge.
+* ``tpm-spapr``: a Trusted Platform Module (TPM).
+* ``spapr-tpm-proxy``: a TPM proxy.
+
+These are compatible with the devices historically available for use when
+running the IBM PowerVM hypervisor with LPARs.
+
+However, since these devices have originally been specified with another
+hypervisor and non-Linux guests in mind, you should use the virtio counterparts
+(virtio-net, virtio-blk/scsi and virtio-rng for instance) if possible instead,
+since they will most probably give you better performance with Linux guests in a
+QEMU environment.
+
+The pSeries machine in QEMU is always instantiated with the following devices:
+
+* A NVRAM device (``spapr-nvram``).
+* A virtual teletype (``spapr-vty``).
+* A PCI host bridge (``spapr-pci-host-bridge``).
+
+Hence, it is not needed to add them manually, unless you use the ``-nodefaults``
+command line option in QEMU.
+
+In the case of the default ``spapr-nvram`` device, if someone wants to make the
+contents of the NVRAM device persistent, they will need to specify a PFLASH
+device when starting QEMU, i.e. either use
+``-drive if=pflash,file=<filename>,format=raw`` to set the default PFLASH
+device, or specify one with an ID
+(``-drive if=none,file=<filename>,format=raw,id=pfid``) and pass that ID to the
+NVRAM device with ``-global spapr-nvram.drive=pfid``.
+
+sPAPR specification
+^^^^^^^^^^^^^^^^^^^
+
+The main source of documentation on the sPAPR standard is the `Linux on Power
+Architecture Reference document (LoPAR)
+<https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_.
+However, documentation specific to QEMU's implementation of the specification
+can also be found in QEMU documentation:
+
+.. toctree::
+ :maxdepth: 1
+
+ ../../specs/ppc-spapr-numa.rst
+ ../../specs/ppc-spapr-xive.rst
+
+Other documentation available in QEMU docs directory:
+
+* Hypervisor calls (a.k.a. hcalls) (``docs/specs/ppc-spapr-hcalls.txt``).
+* Hot plug (``/docs/specs/ppc-spapr-hotplug.txt``).
+* Hypervisor calls needed by the Ultravisor
+ (``/docs/specs/ppc-spapr-uv-hcalls.txt``).
+
+Switching between the KVM-PR and KVM-HV kernel module
+-----------------------------------------------------
+
+Currently, there are two implementations of KVM on Power, ``kvm_hv.ko`` and
+``kvm_pr.ko``.
+
+
+If a host supports both KVM modes, and both KVM kernel modules are loaded, it is
+possible to switch between the two modes with the ``kvm-type`` parameter:
+
+* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=PR`` to use the
+ ``kvm_pr.ko`` kernel module.
+* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=HV`` to use ``kvm_hv.ko``
+ instead.
+
+KVM-PR
+^^^^^^
+
+KVM-PR uses the so-called **PR**\ oblem state of the PPC CPUs to run the guests,
+i.e. the virtual machine is run in user mode and all privileged instructions
+trap and have to be emulated by the host. That means you can run KVM-PR inside
+a pSeries guest (or a PowerVM LPAR for that matter), and that is where it has
+originated, as historically (prior to POWER7) it was not possible to run Linux
+on hypervisor mode on a Power processor (this function was restricted to
+PowerVM, the IBM proprietary hypervisor).
+
+Because all privileged instructions are trapped, guests that use a lot of
+privileged instructions run quite slow with KVM-PR. On the other hand, because
+of that, this kernel module can run on pretty much every PPC hardware, and is
+able to emulate a lot of guests CPUs. This module can even be used to run other
+PowerPC guests like an emulated PowerMac.
+
+As KVM-PR can be run inside a pSeries guest, it can also provide nested
+virtualization capabilities (i.e. running a guest from within a guest).
+
+It is important to notice that, as KVM-HV provides a much better execution
+performance, maintenance work has been much more focused on it in the past
+years. Maintenance for KVM-PR has been minimal.
+
+In order to run KVM-PR guests with POWER9 processors, someone will need to start
+QEMU with ``kernel_irqchip=off`` command line option.
+
+KVM-HV
+^^^^^^
+
+KVM-HV uses the hypervisor mode of more recent Power processors, that allow
+access to the bare metal hardware directly. Although POWER7 had this capability,
+it was only starting with POWER8 that this was officially supported by IBM.
+
+Originally, KVM-HV was only available when running on a PowerNV platform (a.k.a.
+Power bare metal). Although it runs on a PowerNV platform, it can only be used
+to start pSeries guests. As the pSeries guest doesn't have access to the
+hypervisor mode of the Power CPU, it wasn't possible to run KVM-HV on a guest.
+This limitation has been lifted, and now it is possible to run KVM-HV inside
+pSeries guests as well, making nested virtualization possible with KVM-HV.
+
+As KVM-HV has access to privileged instructions, guests that use a lot of these
+can run much faster than with KVM-PR. On the other hand, the guest CPU has to be
+of the same type as the host CPU this way, e.g. it is not possible to specify an
+embedded PPC CPU for the guest with KVM-HV. However, there is at least the
+possibility to run the guest in a backward-compatibility mode of the previous
+CPUs generations, e.g. you can run a POWER7 guest on a POWER8 host by using
+``-cpu POWER8,compat=power7`` as parameter to QEMU.
+
+Modules support
+---------------
+
+As noticed in the sections above, each module can run in a different
+environment. The following table shows with which environment each module can
+run. As long as you are in a supported environment, you can run KVM-PR or KVM-HV
+nested. Combinations not shown in the table are not available.
+
++--------------+------------+------+-------------------+----------+--------+
+| Platform | Host type | Bits | Page table format | KVM-HV | KVM-PR |
++==============+============+======+===================+==========+========+
+| PowerNV | bare metal | 32 | hash | no | yes |
+| | | +-------------------+----------+--------+
+| | | | radix | N/A | N/A |
+| | +------+-------------------+----------+--------+
+| | | 64 | hash | yes | yes |
+| | | +-------------------+----------+--------+
+| | | | radix | yes | no |
++--------------+------------+------+-------------------+----------+--------+
+| pSeries [1]_ | PowerNV | 32 | hash | no | yes |
+| | | +-------------------+----------+--------+
+| | | | radix | N/A | N/A |
+| | +------+-------------------+----------+--------+
+| | | 64 | hash | no | yes |
+| | | +-------------------+----------+--------+
+| | | | radix | yes [2]_ | no |
+| +------------+------+-------------------+----------+--------+
+| | PowerVM | 32 | hash | no | yes |
+| | | +-------------------+----------+--------+
+| | | | radix | N/A | N/A |
+| | +------+-------------------+----------+--------+
+| | | 64 | hash | no | yes |
+| | | +-------------------+----------+--------+
+| | | | radix [3]_ | no | yes |
++--------------+------------+------+-------------------+----------+--------+
+
+.. [1] On POWER9 DD2.1 processors, the page table format on the host and guest
+ must be the same.
+
+.. [2] KVM-HV cannot run nested on POWER8 machines.
+
+.. [3] Introduced on Power10 machines.
+
+Maintainer contact information
+------------------------------
+
+Cédric Le Goater <clg@kaod.org>
+
+Daniel Henrique Barboza <danielhb413@gmail.com>
\ No newline at end of file
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 017/102] docs: rSTify ppc-spapr-hcalls.txt
2021-12-15 17:02 ` Cédric Le Goater
` (2 preceding siblings ...)
2021-12-15 17:02 ` [PULL 016/102] docs: Introducing pseries documentation Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 018/102] docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst Cédric Le Goater
` (84 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Leonardo Garcia, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
From: Leonardo Garcia <lagarcia@br.ibm.com>
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
[ clg: replaced lingua by terminology ]
Message-Id: <e20319dcf0ec37bedd915c740c3813eb0e58ead4.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/specs/ppc-spapr-hcalls.txt | 92 ++++++++++++++++++++-------------
1 file changed, 57 insertions(+), 35 deletions(-)
diff --git a/docs/specs/ppc-spapr-hcalls.txt b/docs/specs/ppc-spapr-hcalls.txt
index 93fe3da91b16..72a768b5a038 100644
--- a/docs/specs/ppc-spapr-hcalls.txt
+++ b/docs/specs/ppc-spapr-hcalls.txt
@@ -1,9 +1,15 @@
-When used with the "pseries" machine type, QEMU-system-ppc64 implements
-a set of hypervisor calls using a subset of the server "PAPR" specification
-(IBM internal at this point), which is also what IBM's proprietary hypervisor
-adheres too.
+sPAPR hypervisor calls
+----------------------
-The subset is selected based on the requirements of Linux as a guest.
+When used with the ``pseries`` machine type, ``qemu-system-ppc64`` implements
+a set of hypervisor calls (a.k.a. hcalls) defined in the `Linux on Power
+Architecture Reference document (LoPAR)
+<https://cdn.openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200812.pdf>`_.
+This document is a subset of the Power Architecture Platform Reference (PAPR+)
+specification (IBM internal only), which is what PowerVM, the IBM proprietary
+hypervisor, adheres to.
+
+The subset in LoPAR is selected based on the requirements of Linux as a guest.
In addition to those calls, we have added our own private hypervisor
calls which are mostly used as a private interface between the firmware
@@ -12,13 +18,14 @@ running in the guest and QEMU.
All those hypercalls start at hcall number 0xf000 which correspond
to an implementation specific range in PAPR.
-- H_RTAS (0xf000)
+H_RTAS (0xf000)
+^^^^^^^^^^^^^^^
-RTAS is a set of runtime services generally provided by the firmware
-inside the guest to the operating system. It predates the existence
-of hypervisors (it was originally an extension to Open Firmware) and
-is still used by PAPR to provide various services that aren't performance
-sensitive.
+RTAS stands for Run-Time Abstraction Sercies and is a set of runtime services
+generally provided by the firmware inside the guest to the operating system. It
+predates the existence of hypervisors (it was originally an extension to Open
+Firmware) and is still used by PAPR and LoPAR to provide various services that
+are not performance sensitive.
We currently implement the RTAS services in QEMU itself. The actual RTAS
"firmware" blob in the guest is a small stub of a few instructions which
@@ -26,22 +33,25 @@ calls our private H_RTAS hypervisor call to pass the RTAS calls to QEMU.
Arguments:
- r3 : H_RTAS (0xf000)
- r4 : Guest physical address of RTAS parameter block
+ ``r3``: ``H_RTAS (0xf000)``
+
+ ``r4``: Guest physical address of RTAS parameter block.
Returns:
- H_SUCCESS : Successfully called the RTAS function (RTAS result
- will have been stored in the parameter block)
- H_PARAMETER : Unknown token
+ ``H_SUCCESS``: Successfully called the RTAS function (RTAS result will have
+ been stored in the parameter block).
-- H_LOGICAL_MEMOP (0xf001)
+ ``H_PARAMETER``: Unknown token.
-When the guest runs in "real mode" (in powerpc lingua this means
-with MMU disabled, ie guest effective == guest physical), it only
-has access to a subset of memory and no IOs.
+H_LOGICAL_MEMOP (0xf001)
+^^^^^^^^^^^^^^^^^^^^^^^^
-PAPR provides a set of hypervisor calls to perform cacheable or
+When the guest runs in "real mode" (in powerpc terminology this means with MMU
+disabled, i.e. guest effective address equals to guest physical address), it
+only has access to a subset of memory and no I/Os.
+
+PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or
non-cacheable accesses to any guest physical addresses that the
guest can use in order to access IO devices while in real mode.
@@ -58,21 +68,33 @@ is used by our SLOF firmware to invert the screen.
Arguments:
- r3: H_LOGICAL_MEMOP (0xf001)
- r4: Guest physical address of destination
- r5: Guest physical address of source
- r6: Individual element size
- 0 = 1 byte
- 1 = 2 bytes
- 2 = 4 bytes
- 3 = 8 bytes
- r7: Number of elements
- r8: Operation
- 0 = copy
- 1 = xor
+ ``r3 ``: ``H_LOGICAL_MEMOP (0xf001)``
+
+ ``r4``: Guest physical address of destination.
+
+ ``r5``: Guest physical address of source.
+
+ ``r6``: Individual element size, defined by the binary logarithm of the
+ desired size. Supported values are:
+
+ ``0`` = 1 byte
+
+ ``1`` = 2 bytes
+
+ ``2`` = 4 bytes
+
+ ``3`` = 8 bytes
+
+ ``r7``: Number of elements.
+
+ ``r8``: Operation. Supported values are:
+
+ ``0``: copy
+
+ ``1``: xor
Returns:
- H_SUCCESS : Success
- H_PARAMETER : Invalid argument
+ ``H_SUCCESS``: Success.
+ ``H_PARAMETER``: Invalid argument.
\ No newline at end of file
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 018/102] docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst.
2021-12-15 17:02 ` Cédric Le Goater
` (3 preceding siblings ...)
2021-12-15 17:02 ` [PULL 017/102] docs: rSTify ppc-spapr-hcalls.txt Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 019/102] Link new ppc-spapr-hcalls.rst file to pseries.rst Cédric Le Goater
` (83 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Leonardo Garcia, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
From: Leonardo Garcia <lagarcia@br.ibm.com>
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} (100%)
diff --git a/docs/specs/ppc-spapr-hcalls.txt b/docs/specs/ppc-spapr-hcalls.rst
similarity index 100%
rename from docs/specs/ppc-spapr-hcalls.txt
rename to docs/specs/ppc-spapr-hcalls.rst
--
2.31.1
^ permalink raw reply [flat|nested] 111+ messages in thread* [PULL 019/102] Link new ppc-spapr-hcalls.rst file to pseries.rst.
2021-12-15 17:02 ` Cédric Le Goater
` (4 preceding siblings ...)
2021-12-15 17:02 ` [PULL 018/102] docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 020/102] softfloat: Extend float_exception_flags to 16 bits Cédric Le Goater
` (82 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Leonardo Garcia, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
From: Leonardo Garcia <lagarcia@br.ibm.com>
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/ppc/pseries.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index e46f09d4c8d7..56f5942e13f6 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -113,12 +113,12 @@ can also be found in QEMU documentation:
.. toctree::
:maxdepth: 1
+ ../../specs/ppc-spapr-hcalls.rst
../../specs/ppc-spapr-numa.rst
../../specs/ppc-spapr-xive.rst
Other documentation available in QEMU docs directory:
-* Hypervisor calls (a.k.a. hcalls) (``docs/specs/ppc-spapr-hcalls.txt``).
* Hot plug (``/docs/specs/ppc-spapr-hotplug.txt``).
* Hypervisor calls needed by the Ultravisor
(``/docs/specs/ppc-spapr-uv-hcalls.txt``).
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 020/102] softfloat: Extend float_exception_flags to 16 bits
2021-12-15 17:02 ` Cédric Le Goater
` (5 preceding siblings ...)
2021-12-15 17:02 ` [PULL 019/102] Link new ppc-spapr-hcalls.rst file to pseries.rst Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 021/102] softfloat: Add flag specific to Inf - Inf Cédric Le Goater
` (81 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Philippe Mathieu-Daudé,
Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 16 ++++++++--------
include/fpu/softfloat.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 5bcbd041f74f..65a43aff5970 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -145,13 +145,13 @@ typedef enum __attribute__((__packed__)) {
*/
enum {
- float_flag_invalid = 1,
- float_flag_divbyzero = 4,
- float_flag_overflow = 8,
- float_flag_underflow = 16,
- float_flag_inexact = 32,
- float_flag_input_denormal = 64,
- float_flag_output_denormal = 128
+ float_flag_invalid = 0x0001,
+ float_flag_divbyzero = 0x0002,
+ float_flag_overflow = 0x0004,
+ float_flag_underflow = 0x0008,
+ float_flag_inexact = 0x0010,
+ float_flag_input_denormal = 0x0020,
+ float_flag_output_denormal = 0x0040,
};
/*
@@ -171,8 +171,8 @@ typedef enum __attribute__((__packed__)) {
*/
typedef struct float_status {
+ uint16_t float_exception_flags;
FloatRoundMode float_rounding_mode;
- uint8_t float_exception_flags;
FloatX80RoundPrec floatx80_rounding_precision;
bool tininess_before_rounding;
/* should denormalised results go to zero and set the inexact flag? */
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index a249991e6127..0d3b40780762 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -100,7 +100,7 @@ typedef enum {
| Routine to raise any or all of the software IEC/IEEE floating-point
| exception flags.
*----------------------------------------------------------------------------*/
-static inline void float_raise(uint8_t flags, float_status *status)
+static inline void float_raise(uint16_t flags, float_status *status)
{
status->float_exception_flags |= flags;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 021/102] softfloat: Add flag specific to Inf - Inf
2021-12-15 17:02 ` Cédric Le Goater
` (6 preceding siblings ...)
2021-12-15 17:02 ` [PULL 020/102] softfloat: Extend float_exception_flags to 16 bits Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 022/102] softfloat: Add flag specific to Inf * 0 Cédric Le Goater
` (80 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 65a43aff5970..eaa12e1e0033 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -152,6 +152,7 @@ enum {
float_flag_inexact = 0x0010,
float_flag_input_denormal = 0x0020,
float_flag_output_denormal = 0x0040,
+ float_flag_invalid_isi = 0x0080, /* inf - inf */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index 41d4b17e4190..eb2b475ca466 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -354,7 +354,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b,
return a;
}
/* Inf - Inf */
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_isi, s);
parts_default_nan(a, s);
return a;
}
@@ -494,6 +494,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
if (ab_mask & float_cmask_inf) {
if (c->cls == float_class_inf && a->sign != c->sign) {
+ float_raise(float_flag_invalid | float_flag_invalid_isi, s);
goto d_nan;
}
goto return_inf;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 022/102] softfloat: Add flag specific to Inf * 0
2021-12-15 17:02 ` Cédric Le Goater
` (7 preceding siblings ...)
2021-12-15 17:02 ` [PULL 021/102] softfloat: Add flag specific to Inf - Inf Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 023/102] softfloat: Add flags specific to Inf / Inf and 0 / 0 Cédric Le Goater
` (79 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 4 ++--
fpu/softfloat-specialize.c.inc | 12 ++++++------
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index eaa12e1e0033..56b4cf783544 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -153,6 +153,7 @@ enum {
float_flag_input_denormal = 0x0020,
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
+ float_flag_invalid_imz = 0x0100, /* inf * 0 */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index eb2b475ca466..3ed793347b18 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b,
/* Inf * Zero == NaN */
if (unlikely(ab_mask == float_cmask_infzero)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
parts_default_nan(a, s);
return a;
}
@@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
if (unlikely(ab_mask != float_cmask_normal)) {
if (unlikely(ab_mask == float_cmask_infzero)) {
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
goto d_nan;
}
@@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,
goto finish_sign;
d_nan:
- float_raise(float_flag_invalid, s);
parts_default_nan(a, s);
return a;
}
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index f2ad0f335e63..943e3301d209 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* the default NaN
*/
if (infzero && is_qnan(c_cls)) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
@@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
/* Prefer sNaN over qNaN, in the a, b, c order. */
@@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the input value 'c'
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
/* Prefer sNaN over qNaN, in the c, a, b order. */
@@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* a default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
@@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
#elif defined(TARGET_RISCV)
/* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
}
return 3; /* default NaN */
#elif defined(TARGET_XTENSA)
@@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* an input NaN if we have one (ie c).
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
if (status->use_first_nan) {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 023/102] softfloat: Add flags specific to Inf / Inf and 0 / 0
2021-12-15 17:02 ` Cédric Le Goater
` (8 preceding siblings ...)
2021-12-15 17:02 ` [PULL 022/102] softfloat: Add flag specific to Inf * 0 Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 024/102] softfloat: Add flag specific to sqrt(-x) Cédric Le Goater
` (78 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 2 ++
fpu/softfloat-parts.c.inc | 16 +++++++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 56b4cf783544..5a9671e564c6 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -154,6 +154,8 @@ enum {
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
float_flag_invalid_imz = 0x0100, /* inf * 0 */
+ float_flag_invalid_idi = 0x0200, /* inf / inf */
+ float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index 3ed793347b18..b8563cd2df8d 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -590,11 +590,13 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,
}
/* 0/0 or Inf/Inf => NaN */
- if (unlikely(ab_mask == float_cmask_zero) ||
- unlikely(ab_mask == float_cmask_inf)) {
- float_raise(float_flag_invalid, s);
- parts_default_nan(a, s);
- return a;
+ if (unlikely(ab_mask == float_cmask_zero)) {
+ float_raise(float_flag_invalid | float_flag_invalid_zdz, s);
+ goto d_nan;
+ }
+ if (unlikely(ab_mask == float_cmask_inf)) {
+ float_raise(float_flag_invalid | float_flag_invalid_idi, s);
+ goto d_nan;
}
/* All the NaN cases */
@@ -625,6 +627,10 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b,
float_raise(float_flag_divbyzero, s);
a->cls = float_class_inf;
return a;
+
+ d_nan:
+ parts_default_nan(a, s);
+ return a;
}
/*
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 024/102] softfloat: Add flag specific to sqrt(-x)
2021-12-15 17:02 ` Cédric Le Goater
` (9 preceding siblings ...)
2021-12-15 17:02 ` [PULL 023/102] softfloat: Add flags specific to Inf / Inf and 0 / 0 Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 025/102] softfloat: Add flag specific to convert non-nan to int Cédric Le Goater
` (77 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 5a9671e564c6..33224b5f227d 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -156,6 +156,7 @@ enum {
float_flag_invalid_imz = 0x0100, /* inf * 0 */
float_flag_invalid_idi = 0x0200, /* inf / inf */
float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
+ float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index b8563cd2df8d..cc8c2c3aee1a 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -869,7 +869,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status,
return;
d_nan:
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_sqrt, status);
parts_default_nan(a, status);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 025/102] softfloat: Add flag specific to convert non-nan to int
2021-12-15 17:02 ` Cédric Le Goater
` (10 preceding siblings ...)
2021-12-15 17:02 ` [PULL 024/102] softfloat: Add flag specific to sqrt(-x) Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 026/102] softfloat: Add flag specific to signaling nans Cédric Le Goater
` (76 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 14 +++++++-------
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 33224b5f227d..9ca50e930b8d 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -157,6 +157,7 @@ enum {
float_flag_invalid_idi = 0x0200, /* inf / inf */
float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */
+ float_flag_invalid_cvti = 0x1000, /* non-nan to integer */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index cc8c2c3aee1a..ce580347dda6 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -1055,7 +1055,7 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,
break;
case float_class_inf:
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = p->sign ? min : max;
break;
@@ -1077,11 +1077,11 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,
if (r <= -(uint64_t)min) {
r = -r;
} else {
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = min;
}
} else if (r > max) {
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
}
break;
@@ -1120,7 +1120,7 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,
break;
case float_class_inf:
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = p->sign ? 0 : max;
break;
@@ -1138,15 +1138,15 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,
}
if (p->sign) {
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = 0;
} else if (p->exp > DECOMPOSED_BINARY_POINT) {
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
} else {
r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp);
if (r > max) {
- flags = float_flag_invalid;
+ flags = float_flag_invalid | float_flag_invalid_cvti;
r = max;
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 026/102] softfloat: Add flag specific to signaling nans
2021-12-15 17:02 ` Cédric Le Goater
` (11 preceding siblings ...)
2021-12-15 17:02 ` [PULL 025/102] softfloat: Add flag specific to convert non-nan to int Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 027/102] target/ppc: Update float_invalid_op_addsub for new flags Cédric Le Goater
` (75 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat.c | 4 +++-
fpu/softfloat-parts.c.inc | 18 ++++++++++++------
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 9ca50e930b8d..8abd9ab4ec9c 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -158,6 +158,7 @@ enum {
float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */
float_flag_invalid_cvti = 0x1000, /* non-nan to integer */
+ float_flag_invalid_snan = 0x2000, /* any operand was snan */
};
/*
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 9a28720d82a5..834ed3a054f7 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2543,8 +2543,10 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status)
static void parts_float_to_ahp(FloatParts64 *a, float_status *s)
{
switch (a->cls) {
- case float_class_qnan:
case float_class_snan:
+ float_raise(float_flag_invalid_snan, s);
+ /* fall through */
+ case float_class_qnan:
/*
* There is no NaN in the destination format. Raise Invalid
* and return a zero with the sign of the input NaN.
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index ce580347dda6..db3e1f393dfb 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -19,7 +19,7 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
{
switch (a->cls) {
case float_class_snan:
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
if (s->default_nan_mode) {
parts_default_nan(a, s);
} else {
@@ -40,7 +40,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
float_status *s)
{
if (is_snan(a->cls) || is_snan(b->cls)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
}
if (s->default_nan_mode) {
@@ -68,7 +68,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
int which;
if (unlikely(abc_mask & float_cmask_snan)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
}
which = pickNaNMulAdd(a->cls, b->cls, c->cls,
@@ -1049,8 +1049,10 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode,
switch (p->cls) {
case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
case float_class_qnan:
- flags = float_flag_invalid;
+ flags |= float_flag_invalid;
r = max;
break;
@@ -1114,8 +1116,10 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode,
switch (p->cls) {
case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
case float_class_qnan:
- flags = float_flag_invalid;
+ flags |= float_flag_invalid;
r = max;
break;
@@ -1341,7 +1345,9 @@ static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b,
}
if (unlikely(ab_mask & float_cmask_anynan)) {
- if (!is_quiet || (ab_mask & float_cmask_snan)) {
+ if (ab_mask & float_cmask_snan) {
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
+ } else if (!is_quiet) {
float_raise(float_flag_invalid, s);
}
return float_relation_unordered;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 027/102] target/ppc: Update float_invalid_op_addsub for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (12 preceding siblings ...)
2021-12-15 17:02 ` [PULL 026/102] softfloat: Add flag specific to signaling nans Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 028/102] target/ppc: Update float_invalid_op_mul " Cédric Le Goater
` (74 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index bb72715827c3..d8ad0250bccd 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -498,13 +498,12 @@ void helper_reset_fpstatus(CPUPPCState *env)
set_float_exception_flags(0, &env->fp_status);
}
-static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
- uintptr_t retaddr, int classes)
+static void float_invalid_op_addsub(CPUPPCState *env, int flags,
+ bool set_fpcc, uintptr_t retaddr)
{
- if ((classes & ~is_neg) == is_inf) {
- /* Magnitude subtraction of infinities */
+ if (flags & float_flag_invalid_isi) {
float_invalid_op_vxisi(env, set_fpcc, retaddr);
- } else if (classes & is_snan) {
+ } else if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
@@ -513,12 +512,10 @@ static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_add(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
@@ -528,12 +525,10 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_sub(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
@@ -1664,9 +1659,8 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- float_invalid_op_addsub(env, sfprf, GETPC(), \
- tp##_classify(xa->fld) | \
- tp##_classify(xb->fld)); \
+ float_invalid_op_addsub(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
\
if (r2sp) { \
@@ -1708,9 +1702,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
@@ -3326,9 +3318,7 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 028/102] target/ppc: Update float_invalid_op_mul for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (13 preceding siblings ...)
2021-12-15 17:02 ` [PULL 027/102] target/ppc: Update float_invalid_op_addsub for new flags Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 029/102] target/ppc: Update float_invalid_op_div " Cédric Le Goater
` (73 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d8ad0250bccd..f02bb3a4afd8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -534,13 +534,12 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
-static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
- uintptr_t retaddr, int classes)
+static void float_invalid_op_mul(CPUPPCState *env, int flags,
+ bool set_fprc, uintptr_t retaddr)
{
- if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) {
- /* Multiplication of zero by infinity */
+ if (flags & float_flag_invalid_imz) {
float_invalid_op_vximz(env, set_fprc, retaddr);
- } else if (classes & is_snan) {
+ } else if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
@@ -549,12 +548,10 @@ static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc,
float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_mul(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- float_invalid_op_mul(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_mul(env, flags, 1, GETPC());
}
return ret;
@@ -1735,9 +1732,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- float_invalid_op_mul(env, sfprf, GETPC(), \
- tp##_classify(xa->fld) | \
- tp##_classify(xb->fld)); \
+ float_invalid_op_mul(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
\
if (r2sp) { \
@@ -1775,9 +1771,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_mul(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 029/102] target/ppc: Update float_invalid_op_div for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (14 preceding siblings ...)
2021-12-15 17:02 ` [PULL 028/102] target/ppc: Update float_invalid_op_mul " Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 030/102] target/ppc: Move float_check_status from FPU_FCTI to translate Cédric Le Goater
` (72 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f02bb3a4afd8..9bcd7abd165f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -557,17 +557,14 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
-static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
- uintptr_t retaddr, int classes)
+static void float_invalid_op_div(CPUPPCState *env, int flags,
+ bool set_fprc, uintptr_t retaddr)
{
- classes &= ~is_neg;
- if (classes == is_inf) {
- /* Division of infinity by infinity */
+ if (flags & float_flag_invalid_idi) {
float_invalid_op_vxidi(env, set_fprc, retaddr);
- } else if (classes == is_zero) {
- /* Division of zero by zero */
+ } else if (flags & float_flag_invalid_zdz) {
float_invalid_op_vxzdz(env, set_fprc, retaddr);
- } else if (classes & is_snan) {
+ } else if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
@@ -576,17 +573,13 @@ static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_div(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status)) {
- if (status & float_flag_invalid) {
- float_invalid_op_div(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
- }
- if (status & float_flag_divbyzero) {
- float_zero_divide_excp(env, GETPC());
- }
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_div(env, flags, 1, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ float_zero_divide_excp(env, GETPC());
}
return ret;
@@ -1803,9 +1796,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- float_invalid_op_div(env, sfprf, GETPC(), \
- tp##_classify(xa->fld) | \
- tp##_classify(xb->fld)); \
+ float_invalid_op_div(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
float_zero_divide_excp(env, GETPC()); \
@@ -1846,9 +1838,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_div(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
}
if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
float_zero_divide_excp(env, GETPC());
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 030/102] target/ppc: Move float_check_status from FPU_FCTI to translate
2021-12-15 17:02 ` Cédric Le Goater
` (15 preceding siblings ...)
2021-12-15 17:02 ` [PULL 029/102] target/ppc: Update float_invalid_op_div " Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 031/102] target/ppc: Update float_invalid_cvt for new flags Cédric Le Goater
` (71 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_helper_* calls in gen_compute_fprf_float64
and protect only the first with set_fprf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 9 +++------
target/ppc/translate/fp-impl.c.inc | 3 ++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9bcd7abd165f..f453b0475116 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -600,12 +600,9 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg) \
uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
int status = get_float_exception_flags(&env->fp_status); \
\
- if (unlikely(status)) { \
- if (status & float_flag_invalid) { \
- float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
- ret = nanval; \
- } \
- do_float_check_status(env, GETPC()); \
+ if (unlikely(status & float_flag_invalid)) { \
+ float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
+ ret = nanval; \
} \
return ret; \
}
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 8afd6a087d1d..0767e45d87d8 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -157,8 +157,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_f##name(t1, cpu_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
- gen_compute_fprf_float64(t1); \
+ gen_helper_compute_fprf_float64(cpu_env, t1); \
} \
+ gen_helper_float_check_status(cpu_env); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 031/102] target/ppc: Update float_invalid_cvt for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (16 preceding siblings ...)
2021-12-15 17:02 ` [PULL 030/102] target/ppc: Move float_check_status from FPU_FCTI to translate Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 032/102] target/ppc: Fix VXCVI return value Cédric Le Goater
` (70 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f453b0475116..be460cc74451 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -585,11 +585,11 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
-static void float_invalid_cvt(CPUPPCState *env, bool set_fprc,
- uintptr_t retaddr, int class1)
+static void float_invalid_cvt(CPUPPCState *env, int flags,
+ bool set_fprc, uintptr_t retaddr)
{
float_invalid_op_vxcvi(env, set_fprc, retaddr);
- if (class1 & is_snan) {
+ if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
@@ -598,10 +598,10 @@ static void float_invalid_cvt(CPUPPCState *env, bool set_fprc,
uint64_t helper_##op(CPUPPCState *env, float64 arg) \
{ \
uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
- int status = get_float_exception_flags(&env->fp_status); \
+ int flags = get_float_exception_flags(&env->fp_status); \
\
- if (unlikely(status & float_flag_invalid)) { \
- float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
+ if (unlikely(flags & float_flag_invalid)) { \
+ float_invalid_cvt(env, flags, 1, GETPC()); \
ret = nanval; \
} \
return ret; \
@@ -2794,7 +2794,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
flags = env->fp_status.float_exception_flags; \
if (unlikely(flags & float_flag_invalid)) { \
- float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
+ float_invalid_cvt(env, flags, 0, GETPC()); \
t.tfld = rnan; \
} \
all_flags |= flags; \
@@ -2837,10 +2837,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
+ int flags; \
\
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
- if (env->fp_status.float_exception_flags & float_flag_invalid) { \
- float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
+ flags = get_float_exception_flags(&env->fp_status); \
+ if (flags & float_flag_invalid) { \
+ float_invalid_cvt(env, flags, 0, GETPC()); \
t.tfld = rnan; \
} \
\
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 032/102] target/ppc: Fix VXCVI return value
2021-12-15 17:02 ` Cédric Le Goater
` (17 preceding siblings ...)
2021-12-15 17:02 ` [PULL 031/102] target/ppc: Update float_invalid_cvt for new flags Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 033/102] target/ppc: Remove inline from do_fri Cédric Le Goater
` (69 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index be460cc74451..d471a0a1b89b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -585,13 +585,20 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
-static void float_invalid_cvt(CPUPPCState *env, int flags,
- bool set_fprc, uintptr_t retaddr)
-{
- float_invalid_op_vxcvi(env, set_fprc, retaddr);
+static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
+ uint64_t ret, uint64_t ret_nan,
+ bool set_fprc, uintptr_t retaddr)
+{
+ /*
+ * VXCVI is different from most in that it sets two exception bits,
+ * VXCVI and VXSNAN for an SNaN input.
+ */
if (flags & float_flag_invalid_snan) {
- float_invalid_op_vxsnan(env, retaddr);
+ env->fpscr |= FP_VXSNAN;
}
+ float_invalid_op_vxcvi(env, set_fprc, retaddr);
+
+ return flags & float_flag_invalid_cvti ? ret : ret_nan;
}
#define FPU_FCTI(op, cvt, nanval) \
@@ -599,10 +606,8 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg) \
{ \
uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
int flags = get_float_exception_flags(&env->fp_status); \
- \
if (unlikely(flags & float_flag_invalid)) { \
- float_invalid_cvt(env, flags, 1, GETPC()); \
- ret = nanval; \
+ ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
} \
return ret; \
}
@@ -2794,8 +2799,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
flags = env->fp_status.float_exception_flags; \
if (unlikely(flags & float_flag_invalid)) { \
- float_invalid_cvt(env, flags, 0, GETPC()); \
- t.tfld = rnan; \
+ t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
} \
all_flags |= flags; \
} \
@@ -2842,8 +2846,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \
t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
flags = get_float_exception_flags(&env->fp_status); \
if (flags & float_flag_invalid) { \
- float_invalid_cvt(env, flags, 0, GETPC()); \
- t.tfld = rnan; \
+ t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
} \
\
*xt = t; \
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 033/102] target/ppc: Remove inline from do_fri
2021-12-15 17:02 ` Cédric Le Goater
` (18 preceding siblings ...)
2021-12-15 17:02 ` [PULL 032/102] target/ppc: Fix VXCVI return value Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 034/102] target/ppc: Use FloatRoundMode in do_fri Cédric Le Goater
` (68 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Philippe Mathieu-Daudé,
Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d471a0a1b89b..f81812e5da75 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -641,8 +641,8 @@ FPU_FCFI(fcfids, int64_to_float32, 1)
FPU_FCFI(fcfidu, uint64_to_float64, 0)
FPU_FCFI(fcfidus, uint64_to_float32, 1)
-static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
- int rounding_mode)
+static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
+ int rounding_mode)
{
CPU_DoubleU farg;
FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 034/102] target/ppc: Use FloatRoundMode in do_fri
2021-12-15 17:02 ` Cédric Le Goater
` (19 preceding siblings ...)
2021-12-15 17:02 ` [PULL 033/102] target/ppc: Remove inline from do_fri Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 035/102] target/ppc: Tidy inexact handling " Cédric Le Goater
` (67 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Philippe Mathieu-Daudé,
Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f81812e5da75..c3e0efe7c312 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -642,7 +642,7 @@ FPU_FCFI(fcfidu, uint64_to_float64, 0)
FPU_FCFI(fcfidus, uint64_to_float32, 1)
static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
- int rounding_mode)
+ FloatRoundMode rounding_mode)
{
CPU_DoubleU farg;
FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 035/102] target/ppc: Tidy inexact handling in do_fri
2021-12-15 17:02 ` Cédric Le Goater
` (20 preceding siblings ...)
2021-12-15 17:02 ` [PULL 034/102] target/ppc: Use FloatRoundMode in do_fri Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 036/102] target/ppc: Clean up do_fri Cédric Le Goater
` (66 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c3e0efe7c312..d4f72c296fad 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -654,16 +654,12 @@ static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
float_invalid_op_vxsnan(env, GETPC());
farg.ll = arg | 0x0008000000000000ULL;
} else {
- int inexact = get_float_exception_flags(&env->fp_status) &
- float_flag_inexact;
set_float_rounding_mode(rounding_mode, &env->fp_status);
farg.ll = float64_round_to_int(farg.d, &env->fp_status);
set_float_rounding_mode(old_rounding_mode, &env->fp_status);
/* fri* does not set FPSCR[XX] */
- if (!inexact) {
- env->fp_status.float_exception_flags &= ~float_flag_inexact;
- }
+ env->fp_status.float_exception_flags &= ~float_flag_inexact;
}
do_float_check_status(env, GETPC());
return farg.ll;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 036/102] target/ppc: Clean up do_fri
2021-12-15 17:02 ` Cédric Le Goater
` (21 preceding siblings ...)
2021-12-15 17:02 ` [PULL 035/102] target/ppc: Tidy inexact handling " Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 037/102] target/ppc: Update fmadd for new flags Cédric Le Goater
` (65 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d4f72c296fad..7716bb15b1d2 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -644,25 +644,23 @@ FPU_FCFI(fcfidus, uint64_to_float32, 1)
static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
FloatRoundMode rounding_mode)
{
- CPU_DoubleU farg;
FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
+ int flags;
- farg.ll = arg;
+ set_float_rounding_mode(rounding_mode, &env->fp_status);
+ arg = float64_round_to_int(arg, &env->fp_status);
+ set_float_rounding_mode(old_rounding_mode, &env->fp_status);
- if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
- /* sNaN round */
+ flags = get_float_exception_flags(&env->fp_status);
+ if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, GETPC());
- farg.ll = arg | 0x0008000000000000ULL;
- } else {
- set_float_rounding_mode(rounding_mode, &env->fp_status);
- farg.ll = float64_round_to_int(farg.d, &env->fp_status);
- set_float_rounding_mode(old_rounding_mode, &env->fp_status);
-
- /* fri* does not set FPSCR[XX] */
- env->fp_status.float_exception_flags &= ~float_flag_inexact;
}
+
+ /* fri* does not set FPSCR[XX] */
+ set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status);
do_float_check_status(env, GETPC());
- return farg.ll;
+
+ return arg;
}
uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 037/102] target/ppc: Update fmadd for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (22 preceding siblings ...)
2021-12-15 17:02 ` [PULL 036/102] target/ppc: Clean up do_fri Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 038/102] target/ppc: Split out do_fmadd Cédric Le Goater
` (64 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd,
whereas the previous *_maddsub_update_excp assumed it true.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 46 ++++++++++-------------------------------
1 file changed, 11 insertions(+), 35 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 7716bb15b1d2..f5d6bb4eba76 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -683,38 +683,15 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
return do_fri(env, arg, float_round_down);
}
-#define FPU_MADDSUB_UPDATE(NAME, TP) \
-static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
- unsigned int madd_flags, uintptr_t retaddr) \
-{ \
- if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
- TP##_is_signaling_nan(arg2, &env->fp_status) || \
- TP##_is_signaling_nan(arg3, &env->fp_status)) { \
- /* sNaN operation */ \
- float_invalid_op_vxsnan(env, retaddr); \
- } \
- if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
- (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
- /* Multiplication of zero by infinity */ \
- float_invalid_op_vximz(env, 1, retaddr); \
- } \
- if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
- TP##_is_infinity(arg3)) { \
- uint8_t aSign, bSign, cSign; \
- \
- aSign = TP##_is_neg(arg1); \
- bSign = TP##_is_neg(arg2); \
- cSign = TP##_is_neg(arg3); \
- if (madd_flags & float_muladd_negate_c) { \
- cSign ^= 1; \
- } \
- if (aSign ^ bSign ^ cSign) { \
- float_invalid_op_vxisi(env, 1, retaddr); \
- } \
- } \
+static void float_invalid_op_madd(CPUPPCState *env, int flags,
+ bool set_fpcc, uintptr_t retaddr)
+{
+ if (flags & float_flag_invalid_imz) {
+ float_invalid_op_vximz(env, set_fpcc, retaddr);
+ } else {
+ float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
+ }
}
-FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
-FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
#define FPU_FMADD(op, madd_flags) \
uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
@@ -726,8 +703,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
flags = get_float_exception_flags(&env->fp_status); \
if (flags) { \
if (flags & float_flag_invalid) { \
- float64_maddsub_update_excp(env, arg1, arg2, arg3, \
- madd_flags, GETPC()); \
+ float_invalid_op_madd(env, flags, 1, GETPC()); \
} \
do_float_check_status(env, GETPC()); \
} \
@@ -2131,8 +2107,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- tp##_maddsub_update_excp(env, xa->fld, b->fld, \
- c->fld, maddflgs, GETPC()); \
+ float_invalid_op_madd(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
\
if (r2sp) { \
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 038/102] target/ppc: Split out do_fmadd
2021-12-15 17:02 ` Cédric Le Goater
` (23 preceding siblings ...)
2021-12-15 17:02 ` [PULL 037/102] target/ppc: Update fmadd for new flags Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 039/102] target/ppc: Do not call do_float_check_status from do_fmadd Cédric Le Goater
` (63 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f5d6bb4eba76..d7e0362e808e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -693,23 +693,26 @@ static void float_invalid_op_madd(CPUPPCState *env, int flags,
}
}
-#define FPU_FMADD(op, madd_flags) \
-uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
- uint64_t arg2, uint64_t arg3) \
-{ \
- uint32_t flags; \
- float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
- &env->fp_status); \
- flags = get_float_exception_flags(&env->fp_status); \
- if (flags) { \
- if (flags & float_flag_invalid) { \
- float_invalid_op_madd(env, flags, 1, GETPC()); \
- } \
- do_float_check_status(env, GETPC()); \
- } \
- return ret; \
+static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
+ float64 c, int madd_flags, uintptr_t retaddr)
+{
+ float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (flags) {
+ if (flags & float_flag_invalid) {
+ float_invalid_op_madd(env, flags, 1, retaddr);
+ }
+ do_float_check_status(env, retaddr);
+ }
+ return ret;
}
+#define FPU_FMADD(op, madd_flags) \
+ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
+ uint64_t arg2, uint64_t arg3) \
+ { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); }
+
#define MADD_FLGS 0
#define MSUB_FLGS float_muladd_negate_c
#define NMADD_FLGS float_muladd_negate_result
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 039/102] target/ppc: Do not call do_float_check_status from do_fmadd
2021-12-15 17:02 ` Cédric Le Goater
` (24 preceding siblings ...)
2021-12-15 17:02 ` [PULL 038/102] target/ppc: Split out do_fmadd Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 040/102] target/ppc: Split out do_frsp Cédric Le Goater
` (62 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d7e0362e808e..dd9d40f74b9b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -699,11 +699,8 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
int flags = get_float_exception_flags(&env->fp_status);
- if (flags) {
- if (flags & float_flag_invalid) {
- float_invalid_op_madd(env, flags, 1, retaddr);
- }
- do_float_check_status(env, retaddr);
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_madd(env, flags, 1, retaddr);
}
return ret;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 040/102] target/ppc: Split out do_frsp
2021-12-15 17:02 ` Cédric Le Goater
` (25 preceding siblings ...)
2021-12-15 17:02 ` [PULL 039/102] target/ppc: Do not call do_float_check_status from do_fmadd Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 041/102] target/ppc: Update do_frsp for new flags Cédric Le Goater
` (61 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index dd9d40f74b9b..77ab6f9e6426 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -721,7 +721,7 @@ FPU_FMADD(fmsub, MSUB_FLGS)
FPU_FMADD(fnmsub, NMSUB_FLGS)
/* frsp - frsp. */
-uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
+static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
{
CPU_DoubleU farg;
float32 f32;
@@ -729,7 +729,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
- float_invalid_op_vxsnan(env, GETPC());
+ float_invalid_op_vxsnan(env, retaddr);
}
f32 = float64_to_float32(farg.d, &env->fp_status);
farg.d = float32_to_float64(f32, &env->fp_status);
@@ -737,6 +737,11 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
return farg.ll;
}
+uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
+{
+ return do_frsp(env, arg, GETPC());
+}
+
/* fsqrt - fsqrt. */
float64 helper_fsqrt(CPUPPCState *env, float64 arg)
{
@@ -1626,7 +1631,7 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -1702,7 +1707,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -1776,7 +1781,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -1844,7 +1849,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -1892,7 +1897,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -1941,7 +1946,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -2112,7 +2117,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
} \
\
if (r2sp) { \
- t.fld = helper_frsp(env, t.fld); \
+ t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
if (sfprf) { \
@@ -2851,7 +2856,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
for (i = 0; i < nels; i++) { \
t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
if (r2sp) { \
- t.tfld = helper_frsp(env, t.tfld); \
+ t.tfld = do_frsp(env, t.tfld, GETPC()); \
} \
if (sfprf) { \
helper_compute_fprf_float64(env, t.tfld); \
@@ -2976,7 +2981,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
{
helper_reset_fpstatus(env);
- uint64_t xt = helper_frsp(env, xb);
+ uint64_t xt = do_frsp(env, xb, GETPC());
helper_compute_fprf_float64(env, xt);
do_float_check_status(env, GETPC());
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 041/102] target/ppc: Update do_frsp for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (26 preceding siblings ...)
2021-12-15 17:02 ` [PULL 040/102] target/ppc: Split out do_frsp Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 042/102] target/ppc: Use helper_todouble in do_frsp Cédric Le Goater
` (60 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 77ab6f9e6426..65acf605b78f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -723,18 +723,13 @@ FPU_FMADD(fnmsub, NMSUB_FLGS)
/* frsp - frsp. */
static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
{
- CPU_DoubleU farg;
- float32 f32;
-
- farg.ll = arg;
+ float32 f32 = float64_to_float32(arg, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
+ if (unlikely(flags & float_flag_invalid_snan)) {
float_invalid_op_vxsnan(env, retaddr);
}
- f32 = float64_to_float32(farg.d, &env->fp_status);
- farg.d = float32_to_float64(f32, &env->fp_status);
-
- return farg.ll;
+ return float32_to_float64(f32, &env->fp_status);
}
uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 042/102] target/ppc: Use helper_todouble in do_frsp
2021-12-15 17:02 ` Cédric Le Goater
` (27 preceding siblings ...)
2021-12-15 17:02 ` [PULL 041/102] target/ppc: Update do_frsp for new flags Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 043/102] target/ppc: Update sqrt for new flags Cédric Le Goater
` (59 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 65acf605b78f..870a861e36a2 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -729,7 +729,7 @@ static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
if (unlikely(flags & float_flag_invalid_snan)) {
float_invalid_op_vxsnan(env, retaddr);
}
- return float32_to_float64(f32, &env->fp_status);
+ return helper_todouble(f32);
}
uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 043/102] target/ppc: Update sqrt for new flags
2021-12-15 17:02 ` Cédric Le Goater
` (28 preceding siblings ...)
2021-12-15 17:02 ` [PULL 042/102] target/ppc: Use helper_todouble in do_frsp Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:02 ` [PULL 044/102] target/ppc: Update xsrqpi and xsrqpxp to " Cédric Le Goater
` (58 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 72 ++++++++++++++---------------------------
1 file changed, 25 insertions(+), 47 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 870a861e36a2..08f7c8837e17 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -737,22 +737,24 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
return do_frsp(env, arg, GETPC());
}
+static void float_invalid_op_sqrt(CPUPPCState *env, int flags,
+ bool set_fpcc, uintptr_t retaddr)
+{
+ if (unlikely(flags & float_flag_invalid_sqrt)) {
+ float_invalid_op_vxsqrt(env, set_fpcc, retaddr);
+ } else if (unlikely(flags & float_flag_invalid_snan)) {
+ float_invalid_op_vxsnan(env, retaddr);
+ }
+}
+
/* fsqrt - fsqrt. */
float64 helper_fsqrt(CPUPPCState *env, float64 arg)
{
float64 ret = float64_sqrt(arg, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- if (unlikely(float64_is_any_nan(arg))) {
- if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) {
- /* sNaN square root */
- float_invalid_op_vxsnan(env, GETPC());
- }
- } else {
- /* Square root of a negative nonzero number */
- float_invalid_op_vxsqrt(env, 1, GETPC());
- }
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_sqrt(env, flags, 1, GETPC());
}
return ret;
@@ -807,22 +809,14 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg)
/* "Estimate" the reciprocal with actual division. */
float64 rets = float64_sqrt(arg, &env->fp_status);
float64 retd = float64_div(float64_one, rets, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status)) {
- if (status & float_flag_invalid) {
- if (float64_is_signaling_nan(arg, &env->fp_status)) {
- /* sNaN reciprocal */
- float_invalid_op_vxsnan(env, GETPC());
- } else {
- /* Square root of a negative nonzero number */
- float_invalid_op_vxsqrt(env, 1, GETPC());
- }
- }
- if (status & float_flag_divbyzero) {
- /* Reciprocal of (square root of) zero. */
- float_zero_divide_excp(env, GETPC());
- }
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_sqrt(env, flags, 1, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ /* Reciprocal of (square root of) zero. */
+ float_zero_divide_excp(env, GETPC());
}
return retd;
@@ -1884,11 +1878,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
- float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
- } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
+ float_invalid_op_sqrt(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
\
if (r2sp) { \
@@ -1931,15 +1922,10 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
t.fld = tp##_sqrt(xb->fld, &tstat); \
t.fld = tp##_div(tp##_one, t.fld, &tstat); \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
- \
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
- float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
- } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
+ float_invalid_op_sqrt(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
- \
if (r2sp) { \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
@@ -3240,15 +3226,7 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- if (float128_is_signaling_nan(xb->f128, &tstat)) {
- float_invalid_op_vxsnan(env, GETPC());
- t.f128 = float128_snan_to_qnan(xb->f128);
- } else if (float128_is_quiet_nan(xb->f128, &tstat)) {
- t.f128 = xb->f128;
- } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) {
- float_invalid_op_vxsqrt(env, 1, GETPC());
- t.f128 = float128_default_nan(&env->fp_status);
- }
+ float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 044/102] target/ppc: Update xsrqpi and xsrqpxp to new flags
2021-12-15 17:02 ` Cédric Le Goater
` (29 preceding siblings ...)
2021-12-15 17:02 ` [PULL 043/102] target/ppc: Update sqrt for new flags Cédric Le Goater
@ 2021-12-15 17:02 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 045/102] target/ppc: Update fre " Cédric Le Goater
` (57 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:02 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 08f7c8837e17..853e0aad1d4e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3138,11 +3138,8 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
t.f128 = float128_round_to_int(xb->f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
- if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- if (float128_is_signaling_nan(xb->f128, &tstat)) {
- float_invalid_op_vxsnan(env, GETPC());
- t.f128 = float128_snan_to_qnan(t.f128);
- }
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
+ float_invalid_op_vxsnan(env, GETPC());
}
if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
@@ -3196,11 +3193,9 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
t.f128 = floatx80_to_float128(round_res, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
- if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- if (float128_is_signaling_nan(xb->f128, &tstat)) {
- float_invalid_op_vxsnan(env, GETPC());
- t.f128 = float128_snan_to_qnan(t.f128);
- }
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
+ float_invalid_op_vxsnan(env, GETPC());
+ t.f128 = float128_snan_to_qnan(t.f128);
}
helper_compute_fprf_float128(env, t.f128);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 045/102] target/ppc: Update fre to new flags
2021-12-15 17:02 ` Cédric Le Goater
` (30 preceding siblings ...)
2021-12-15 17:02 ` [PULL 044/102] target/ppc: Update xsrqpi and xsrqpxp to " Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 046/102] softfloat: Add float64r32 arithmetic routines Cédric Le Goater
` (56 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 853e0aad1d4e..aef81a818f63 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -765,20 +765,15 @@ float64 helper_fre(CPUPPCState *env, float64 arg)
{
/* "Estimate" the reciprocal with actual division. */
float64 ret = float64_div(float64_one, arg, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status)) {
- if (status & float_flag_invalid) {
- if (float64_is_signaling_nan(arg, &env->fp_status)) {
- /* sNaN reciprocal */
- float_invalid_op_vxsnan(env, GETPC());
- }
- }
- if (status & float_flag_divbyzero) {
- float_zero_divide_excp(env, GETPC());
- /* For FPSCR.ZE == 0, the result is 1/2. */
- ret = float64_set_sign(float64_half, float64_is_neg(arg));
- }
+ if (unlikely(flags & float_flag_invalid_snan)) {
+ float_invalid_op_vxsnan(env, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ float_zero_divide_excp(env, GETPC());
+ /* For FPSCR.ZE == 0, the result is 1/2. */
+ ret = float64_set_sign(float64_half, float64_is_neg(arg));
}
return ret;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 046/102] softfloat: Add float64r32 arithmetic routines
2021-12-15 17:02 ` Cédric Le Goater
` (31 preceding siblings ...)
2021-12-15 17:03 ` [PULL 045/102] target/ppc: Update fre " Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 047/102] target/ppc: Add helpers for fmadds et al Cédric Le Goater
` (55 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its float32 operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/fpu/softfloat.h | 12 +++++
fpu/softfloat.c | 110 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 0d3b40780762..d34b2c44d256 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -908,6 +908,18 @@ static inline bool float64_unordered_quiet(float64 a, float64 b,
*----------------------------------------------------------------------------*/
float64 float64_default_nan(float_status *status);
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE double-precision operations, rounding to single precision,
+| returning a result in double precision, with only one rounding step.
+*----------------------------------------------------------------------------*/
+
+float64 float64r32_add(float64, float64, float_status *status);
+float64 float64r32_sub(float64, float64, float_status *status);
+float64 float64r32_mul(float64, float64, float_status *status);
+float64 float64r32_div(float64, float64, float_status *status);
+float64 float64r32_muladd(float64, float64, float64, int, float_status *status);
+float64 float64r32_sqrt(float64, float_status *status);
+
/*----------------------------------------------------------------------------
| Software IEC/IEEE extended double-precision conversion routines.
*----------------------------------------------------------------------------*/
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 834ed3a054f7..7f524d437767 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1693,6 +1693,50 @@ static float64 float64_round_pack_canonical(FloatParts64 *p,
return float64_pack_raw(p);
}
+static float64 float64r32_round_pack_canonical(FloatParts64 *p,
+ float_status *s)
+{
+ parts_uncanon(p, s, &float32_params);
+
+ /*
+ * In parts_uncanon, we placed the fraction for float32 at the lsb.
+ * We need to adjust the fraction higher so that the least N bits are
+ * zero, and the fraction is adjacent to the float64 implicit bit.
+ */
+ switch (p->cls) {
+ case float_class_normal:
+ if (unlikely(p->exp == 0)) {
+ /*
+ * The result is denormal for float32, but can be represented
+ * in normalized form for float64. Adjust, per canonicalize.
+ */
+ int shift = frac_normalize(p);
+ p->exp = (float32_params.frac_shift -
+ float32_params.exp_bias - shift + 1 +
+ float64_params.exp_bias);
+ frac_shr(p, float64_params.frac_shift);
+ } else {
+ frac_shl(p, float32_params.frac_shift - float64_params.frac_shift);
+ p->exp += float64_params.exp_bias - float32_params.exp_bias;
+ }
+ break;
+ case float_class_snan:
+ case float_class_qnan:
+ frac_shl(p, float32_params.frac_shift - float64_params.frac_shift);
+ p->exp = float64_params.exp_max;
+ break;
+ case float_class_inf:
+ p->exp = float64_params.exp_max;
+ break;
+ case float_class_zero:
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return float64_pack_raw(p);
+}
+
static void float128_unpack_canonical(FloatParts128 *p, float128 f,
float_status *s)
{
@@ -1938,6 +1982,28 @@ float64_sub(float64 a, float64 b, float_status *s)
return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub);
}
+static float64 float64r32_addsub(float64 a, float64 b, float_status *status,
+ bool subtract)
+{
+ FloatParts64 pa, pb, *pr;
+
+ float64_unpack_canonical(&pa, a, status);
+ float64_unpack_canonical(&pb, b, status);
+ pr = parts_addsub(&pa, &pb, status, subtract);
+
+ return float64r32_round_pack_canonical(pr, status);
+}
+
+float64 float64r32_add(float64 a, float64 b, float_status *status)
+{
+ return float64r32_addsub(a, b, status, false);
+}
+
+float64 float64r32_sub(float64 a, float64 b, float_status *status)
+{
+ return float64r32_addsub(a, b, status, true);
+}
+
static bfloat16 QEMU_FLATTEN
bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtract)
{
@@ -2069,6 +2135,17 @@ float64_mul(float64 a, float64 b, float_status *s)
f64_is_zon2, f64_addsubmul_post);
}
+float64 float64r32_mul(float64 a, float64 b, float_status *status)
+{
+ FloatParts64 pa, pb, *pr;
+
+ float64_unpack_canonical(&pa, a, status);
+ float64_unpack_canonical(&pb, b, status);
+ pr = parts_mul(&pa, &pb, status);
+
+ return float64r32_round_pack_canonical(pr, status);
+}
+
bfloat16 QEMU_FLATTEN
bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status)
{
@@ -2296,6 +2373,19 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s)
return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s);
}
+float64 float64r32_muladd(float64 a, float64 b, float64 c,
+ int flags, float_status *status)
+{
+ FloatParts64 pa, pb, pc, *pr;
+
+ float64_unpack_canonical(&pa, a, status);
+ float64_unpack_canonical(&pb, b, status);
+ float64_unpack_canonical(&pc, c, status);
+ pr = parts_muladd(&pa, &pb, &pc, flags, status);
+
+ return float64r32_round_pack_canonical(pr, status);
+}
+
bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c,
int flags, float_status *status)
{
@@ -2419,6 +2509,17 @@ float64_div(float64 a, float64 b, float_status *s)
f64_div_pre, f64_div_post);
}
+float64 float64r32_div(float64 a, float64 b, float_status *status)
+{
+ FloatParts64 pa, pb, *pr;
+
+ float64_unpack_canonical(&pa, a, status);
+ float64_unpack_canonical(&pb, b, status);
+ pr = parts_div(&pa, &pb, status);
+
+ return float64r32_round_pack_canonical(pr, status);
+}
+
bfloat16 QEMU_FLATTEN
bfloat16_div(bfloat16 a, bfloat16 b, float_status *status)
{
@@ -4285,6 +4386,15 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s)
return soft_f64_sqrt(ua.s, s);
}
+float64 float64r32_sqrt(float64 a, float_status *status)
+{
+ FloatParts64 p;
+
+ float64_unpack_canonical(&p, a, status);
+ parts_sqrt(&p, status, &float64_params);
+ return float64r32_round_pack_canonical(&p, status);
+}
+
bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status)
{
FloatParts64 p;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 047/102] target/ppc: Add helpers for fmadds et al
2021-12-15 17:02 ` Cédric Le Goater
` (32 preceding siblings ...)
2021-12-15 17:03 ` [PULL 046/102] softfloat: Add float64r32 arithmetic routines Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 048/102] target/ppc: Add helper for fsqrts Cédric Le Goater
` (54 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 4 ++++
target/ppc/fpu_helper.c | 17 ++++++++++++++++-
target/ppc/translate/fp-impl.c.inc | 13 +++++--------
3 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 632a81c6766f..8a9f2ee7ed4f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -101,6 +101,10 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64)
+DEF_HELPER_4(fmadds, i64, env, i64, i64, i64)
+DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64)
+DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64)
+DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64)
DEF_HELPER_2(fsqrt, f64, env, f64)
DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index aef81a818f63..12dd889fb5f8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -705,10 +705,25 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
return ret;
}
+static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b,
+ float64 c, int madd_flags, uintptr_t retaddr)
+{
+ float64 ret = float64r32_muladd(a, b, c, madd_flags, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_madd(env, flags, 1, retaddr);
+ }
+ return ret;
+}
+
#define FPU_FMADD(op, madd_flags) \
uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
uint64_t arg2, uint64_t arg3) \
- { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); }
+ { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } \
+ uint64_t helper_##op##s(CPUPPCState *env, uint64_t arg1, \
+ uint64_t arg2, uint64_t arg3) \
+ { return do_fmadds(env, arg1, arg2, arg3, madd_flags, GETPC()); }
#define MADD_FLGS 0
#define MSUB_FLGS float_muladd_negate_c
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 0767e45d87d8..2e3162d3e7c0 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -31,7 +31,7 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx)
#endif
/*** Floating-Point arithmetic ***/
-#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
+#define _GEN_FLOAT_ACB(name, op1, op2, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
@@ -50,10 +50,7 @@ static void gen_f##name(DisasContext *ctx) \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
get_fpr(t2, rB(ctx->opcode)); \
- gen_helper_f##op(t3, cpu_env, t0, t1, t2); \
- if (isfloat) { \
- gen_helper_frsp(t3, cpu_env, t3); \
- } \
+ gen_helper_f##name(t3, cpu_env, t0, t1, t2); \
set_fpr(rD(ctx->opcode), t3); \
if (set_fprf) { \
gen_compute_fprf_float64(t3); \
@@ -68,8 +65,8 @@ static void gen_f##name(DisasContext *ctx) \
}
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
-_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
-_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
+_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \
+_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type);
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
@@ -233,7 +230,7 @@ static void gen_frsqrtes(DisasContext *ctx)
}
/* fsel */
-_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
+_GEN_FLOAT_ACB(sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
/* fsub - fsubs */
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
/* Optional: */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 048/102] target/ppc: Add helper for fsqrts
2021-12-15 17:02 ` Cédric Le Goater
` (33 preceding siblings ...)
2021-12-15 17:03 ` [PULL 047/102] target/ppc: Add helpers for fmadds et al Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 049/102] target/ppc: Add helpers for fadds, fsubs, fdivs Cédric Le Goater
` (53 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/fpu_helper.c | 12 ++++++++++++
target/ppc/translate/fp-impl.c.inc | 3 +--
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8a9f2ee7ed4f..9d7c9a919a98 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -106,6 +106,7 @@ DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64)
DEF_HELPER_2(fsqrt, f64, env, f64)
+DEF_HELPER_2(fsqrts, f64, env, f64)
DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 12dd889fb5f8..07e1695b07b7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -775,6 +775,18 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg)
return ret;
}
+/* fsqrts - fsqrts. */
+float64 helper_fsqrts(CPUPPCState *env, float64 arg)
+{
+ float64 ret = float64r32_sqrt(arg, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_sqrt(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
/* fre - fre. */
float64 helper_fre(CPUPPCState *env, float64 arg)
{
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 2e3162d3e7c0..baa31d3431c7 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -270,8 +270,7 @@ static void gen_fsqrts(DisasContext *ctx)
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode));
- gen_helper_fsqrt(t1, cpu_env, t0);
- gen_helper_frsp(t1, cpu_env, t1);
+ gen_helper_fsqrts(t1, cpu_env, t0);
set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 049/102] target/ppc: Add helpers for fadds, fsubs, fdivs
2021-12-15 17:02 ` Cédric Le Goater
` (34 preceding siblings ...)
2021-12-15 17:03 ` [PULL 048/102] target/ppc: Add helper for fsqrts Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 050/102] target/ppc: Add helper for fmuls Cédric Le Goater
` (52 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 3 +++
target/ppc/fpu_helper.c | 40 ++++++++++++++++++++++++++++++
target/ppc/translate/fp-impl.c.inc | 11 +++-----
3 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9d7c9a919a98..2b80c2f22835 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -94,9 +94,12 @@ DEF_HELPER_2(frip, i64, env, i64)
DEF_HELPER_2(frim, i64, env, i64)
DEF_HELPER_3(fadd, f64, env, f64, f64)
+DEF_HELPER_3(fadds, f64, env, f64, f64)
DEF_HELPER_3(fsub, f64, env, f64, f64)
+DEF_HELPER_3(fsubs, f64, env, f64, f64)
DEF_HELPER_3(fmul, f64, env, f64, f64)
DEF_HELPER_3(fdiv, f64, env, f64, f64)
+DEF_HELPER_3(fdivs, f64, env, f64, f64)
DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 07e1695b07b7..c36cf05d8098 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -521,6 +521,18 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
+/* fadds - fadds. */
+float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_add(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
/* fsub - fsub. */
float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
{
@@ -534,6 +546,18 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
+/* fsubs - fsubs. */
+float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_sub(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
static void float_invalid_op_mul(CPUPPCState *env, int flags,
bool set_fprc, uintptr_t retaddr)
{
@@ -585,6 +609,22 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
+/* fdivs - fdivs. */
+float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_div(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_div(env, flags, 1, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ float_zero_divide_excp(env, GETPC());
+ }
+
+ return ret;
+}
+
static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
uint64_t ret, uint64_t ret_nan,
bool set_fprc, uintptr_t retaddr)
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index baa31d3431c7..b84097544f62 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -68,7 +68,7 @@ static void gen_f##name(DisasContext *ctx) \
_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \
_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type);
-#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+#define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
@@ -84,10 +84,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \
- gen_helper_f##op(t2, cpu_env, t0, t1); \
- if (isfloat) { \
- gen_helper_frsp(t2, cpu_env, t2); \
- } \
+ gen_helper_f##name(t2, cpu_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
@@ -100,8 +97,8 @@ static void gen_f##name(DisasContext *ctx) \
tcg_temp_free_i64(t2); \
}
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
-_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
+_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 050/102] target/ppc: Add helper for fmuls
2021-12-15 17:02 ` Cédric Le Goater
` (35 preceding siblings ...)
2021-12-15 17:03 ` [PULL 049/102] target/ppc: Add helpers for fadds, fsubs, fdivs Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 051/102] target/ppc: Add helper for frsqrtes Cédric Le Goater
` (51 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/fpu_helper.c | 12 ++++++++++++
target/ppc/translate/fp-impl.c.inc | 11 ++++-------
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2b80c2f22835..f70a3aefcbf4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -98,6 +98,7 @@ DEF_HELPER_3(fadds, f64, env, f64, f64)
DEF_HELPER_3(fsub, f64, env, f64, f64)
DEF_HELPER_3(fsubs, f64, env, f64, f64)
DEF_HELPER_3(fmul, f64, env, f64, f64)
+DEF_HELPER_3(fmuls, f64, env, f64, f64)
DEF_HELPER_3(fdiv, f64, env, f64, f64)
DEF_HELPER_3(fdivs, f64, env, f64, f64)
DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c36cf05d8098..4acc557c088a 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -581,6 +581,18 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}
+/* fmuls - fmuls. */
+float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+ float64 ret = float64r32_mul(arg1, arg2, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_mul(env, flags, 1, GETPC());
+ }
+ return ret;
+}
+
static void float_invalid_op_div(CPUPPCState *env, int flags,
bool set_fprc, uintptr_t retaddr)
{
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index b84097544f62..bf56e35cb686 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx) \
_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \
_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
-#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
+#define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
@@ -116,10 +116,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
- gen_helper_f##op(t2, cpu_env, t0, t1); \
- if (isfloat) { \
- gen_helper_frsp(t2, cpu_env, t2); \
- } \
+ gen_helper_f##name(t2, cpu_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
@@ -132,8 +129,8 @@ static void gen_f##name(DisasContext *ctx) \
tcg_temp_free_i64(t2); \
}
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
-_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
-_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \
+_GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type);
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 051/102] target/ppc: Add helper for frsqrtes
2021-12-15 17:02 ` Cédric Le Goater
` (36 preceding siblings ...)
2021-12-15 17:03 ` [PULL 050/102] target/ppc: Add helper for fmuls Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 052/102] target/ppc: Update fres to new flags and float64r32 Cédric Le Goater
` (50 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/fpu_helper.c | 19 +++++++++++++++++++
target/ppc/translate/fp-impl.c.inc | 3 +--
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f70a3aefcbf4..48774fab1917 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -114,6 +114,7 @@ DEF_HELPER_2(fsqrts, f64, env, f64)
DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
DEF_HELPER_2(frsqrte, i64, env, i64)
+DEF_HELPER_2(frsqrtes, i64, env, i64)
DEF_HELPER_4(fsel, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4acc557c088a..83c8f2556cc7 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -896,6 +896,25 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg)
return retd;
}
+/* frsqrtes - frsqrtes. */
+float64 helper_frsqrtes(CPUPPCState *env, float64 arg)
+{
+ /* "Estimate" the reciprocal with actual division. */
+ float64 rets = float64_sqrt(arg, &env->fp_status);
+ float64 retd = float64r32_div(float64_one, rets, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
+
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_sqrt(env, flags, 1, GETPC());
+ }
+ if (unlikely(flags & float_flag_divbyzero)) {
+ /* Reciprocal of (square root of) zero. */
+ float_zero_divide_excp(env, GETPC());
+ }
+
+ return retd;
+}
+
/* fsel - fsel. */
uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
uint64_t arg3)
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index bf56e35cb686..2baae5988fde 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -212,8 +212,7 @@ static void gen_frsqrtes(DisasContext *ctx)
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode));
- gen_helper_frsqrte(t1, cpu_env, t0);
- gen_helper_frsp(t1, cpu_env, t1);
+ gen_helper_frsqrtes(t1, cpu_env, t0);
set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 052/102] target/ppc: Update fres to new flags and float64r32
2021-12-15 17:02 ` Cédric Le Goater
` (37 preceding siblings ...)
2021-12-15 17:03 ` [PULL 051/102] target/ppc: Add helper for frsqrtes Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 053/102] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp Cédric Le Goater
` (49 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 83c8f2556cc7..c955b20739ac 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -861,20 +861,20 @@ float64 helper_fre(CPUPPCState *env, float64 arg)
/* fres - fres. */
uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
{
- CPU_DoubleU farg;
- float32 f32;
-
- farg.ll = arg;
+ /* "Estimate" the reciprocal with actual division. */
+ float64 ret = float64r32_div(float64_one, arg, &env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
- /* sNaN reciprocal */
+ if (unlikely(flags & float_flag_invalid_snan)) {
float_invalid_op_vxsnan(env, GETPC());
}
- farg.d = float64_div(float64_one, farg.d, &env->fp_status);
- f32 = float64_to_float32(farg.d, &env->fp_status);
- farg.d = float32_to_float64(f32, &env->fp_status);
+ if (unlikely(flags & float_flag_divbyzero)) {
+ float_zero_divide_excp(env, GETPC());
+ /* For FPSCR.ZE == 0, the result is 1/2. */
+ ret = float64_set_sign(float64_half, float64_is_neg(arg));
+ }
- return farg.ll;
+ return ret;
}
/* frsqrte - frsqrte. */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 053/102] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
2021-12-15 17:02 ` Cédric Le Goater
` (38 preceding siblings ...)
2021-12-15 17:03 ` [PULL 052/102] target/ppc: Update fres to new flags and float64r32 Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 054/102] target/ppc: Disable software TLB for the 7450 family Cédric Le Goater
` (48 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only ones set within the register, and then a bitwise equality.
Fixes a bug in which a single-precision NaN is considered !SP,
because float64_eq(nan, nan) is always false.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c955b20739ac..1e9a16154036 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3163,26 +3163,25 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
{
uint32_t dcmx, sign, exp;
uint32_t cc, match = 0, not_sp = 0;
+ float64 arg = xb->VsrD(0);
+ float64 arg_sp;
dcmx = DCMX(opcode);
- exp = (xb->VsrD(0) >> 52) & 0x7FF;
+ exp = (arg >> 52) & 0x7FF;
+ sign = float64_is_neg(arg);
- sign = float64_is_neg(xb->VsrD(0));
- if (float64_is_any_nan(xb->VsrD(0))) {
+ if (float64_is_any_nan(arg)) {
match = extract32(dcmx, 6, 1);
- } else if (float64_is_infinity(xb->VsrD(0))) {
+ } else if (float64_is_infinity(arg)) {
match = extract32(dcmx, 4 + !sign, 1);
- } else if (float64_is_zero(xb->VsrD(0))) {
+ } else if (float64_is_zero(arg)) {
match = extract32(dcmx, 2 + !sign, 1);
- } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
- (exp > 0 && exp < 0x381)) {
+ } else if (float64_is_zero_or_denormal(arg) || (exp > 0 && exp < 0x381)) {
match = extract32(dcmx, 0 + !sign, 1);
}
- not_sp = !float64_eq(xb->VsrD(0),
- float32_to_float64(
- float64_to_float32(xb->VsrD(0), &env->fp_status),
- &env->fp_status), &env->fp_status);
+ arg_sp = helper_todouble(helper_tosingle(arg));
+ not_sp = arg != arg_sp;
cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
env->fpscr &= ~FP_FPCC;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 054/102] target/ppc: Disable software TLB for the 7450 family
2021-12-15 17:02 ` Cédric Le Goater
` (39 preceding siblings ...)
2021-12-15 17:03 ` [PULL 053/102] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 055/102] target/ppc: Disable unused facilities in the e600 CPU Cédric Le Goater
` (47 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
3.15. With no known support in firmware or OS, this means that no code
for any of the 7450 CPUs is ever ran in QEMU.
Since the implementation in QEMU of the 7400 MMU is the same as the
7450, except for the software TLB vs. hardware TLB search, this patch
changes all 7450 cpus to the 7400 MMU model. This has the practical
effect of disabling the software TLB feature while keeping other
aspects of address translation working as expected.
This allow us to run software on the 7450 family again.
*- note that the 7448 is currently aliased in QEMU for a 7400, so it
is unaffected by this change.
1- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6695985e9b56..509df35d0907 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5932,7 +5932,6 @@ static void init_proc_7440(CPUPPCState *env)
0x00000000);
/* Memory management */
register_low_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -5956,7 +5955,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -5976,7 +5975,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6067,7 +6066,6 @@ static void init_proc_7450(CPUPPCState *env)
0x00000000);
/* Memory management */
register_low_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6091,7 +6089,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6111,7 +6109,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6205,7 +6203,6 @@ static void init_proc_7445(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6229,7 +6226,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6249,7 +6246,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6345,7 +6342,6 @@ static void init_proc_7455(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6369,7 +6365,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6389,7 +6385,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
@@ -6509,7 +6505,6 @@ static void init_proc_7457(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6533,7 +6528,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->msr_mask = (1ull << MSR_VR) |
@@ -6553,7 +6548,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
+ pcc->mmu_model = POWERPC_MMU_32B;
pcc->excp_model = POWERPC_EXCP_74xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_7400;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 055/102] target/ppc: Disable unused facilities in the e600 CPU
2021-12-15 17:02 ` Cédric Le Goater
` (40 preceding siblings ...)
2021-12-15 17:03 ` [PULL 054/102] target/ppc: Disable software TLB for the 7450 family Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 056/102] target/ppc: Remove the software TLB model of 7450 CPUs Cédric Le Goater
` (46 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 509df35d0907..962acf295fd1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2537,9 +2537,6 @@ static void init_excp_7450(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
- env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
- env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
@@ -6643,7 +6640,6 @@ static void init_proc_e600(CPUPPCState *env)
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
- register_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
@@ -6667,7 +6663,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_MEM_TLBIA | PPC_74xx_TLB |
+ PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
pcc->insns_flags2 = PPC_NONE;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 056/102] target/ppc: Remove the software TLB model of 7450 CPUs
2021-12-15 17:02 ` Cédric Le Goater
` (41 preceding siblings ...)
2021-12-15 17:03 ` [PULL 055/102] target/ppc: Disable unused facilities in the e600 CPU Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 057/102] target/ppc: Fix MPCxxx FPU interrupt address Cédric Le Goater
` (45 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu-qom.h | 6 +++++-
target/ppc/cpu.h | 4 +---
target/ppc/helper.h | 2 --
target/ppc/cpu_init.c | 26 --------------------------
target/ppc/excp_helper.c | 29 -----------------------------
target/ppc/mmu_common.c | 19 -------------------
target/ppc/mmu_helper.c | 31 -------------------------------
target/ppc/translate.c | 26 --------------------------
8 files changed, 6 insertions(+), 137 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 5800fa324e82..ef9e32447473 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -45,7 +45,11 @@ enum powerpc_mmu_t {
POWERPC_MMU_32B = 0x00000001,
/* PowerPC 6xx MMU with software TLB */
POWERPC_MMU_SOFT_6xx = 0x00000002,
- /* PowerPC 74xx MMU with software TLB */
+ /*
+ * PowerPC 74xx MMU with software TLB (this has been
+ * disabled, see git history for more information.
+ * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
+ */
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 441d3dce194c..c07a8e9f7d4b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2142,8 +2142,6 @@ enum {
PPC_SEGMENT = 0x0000020000000000ULL,
/* PowerPC 6xx TLB management instructions */
PPC_6xx_TLB = 0x0000040000000000ULL,
- /* PowerPC 74xx TLB management instructions */
- PPC_74xx_TLB = 0x0000080000000000ULL,
/* PowerPC 40x TLB management instructions */
PPC_40x_TLB = 0x0000100000000000ULL,
/* segment register access instructions for PowerPC 64 "bridge" */
@@ -2200,7 +2198,7 @@ enum {
| PPC_CACHE_DCBZ \
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
- | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
+ | PPC_40x_TLB | PPC_SEGMENT_64B \
| PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 48774fab1917..72b2c70ac1fc 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -625,8 +625,6 @@ DEF_HELPER_2(booke_set_eplc, void, env, tl)
DEF_HELPER_2(booke_set_epsc, void, env, tl)
DEF_HELPER_2(6xx_tlbd, void, env, tl)
DEF_HELPER_2(6xx_tlbi, void, env, tl)
-DEF_HELPER_2(74xx_tlbd, void, env, tl)
-DEF_HELPER_2(74xx_tlbi, void, env, tl)
DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 962acf295fd1..ed0e2136d9c8 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -945,31 +945,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = nb_tlbs;
- env->nb_ways = nb_ways;
- env->id_tlbs = 1;
- env->tlb_type = TLB_6XX;
- /* XXX : not implemented */
- spr_register(env, SPR_PTEHI, "PTEHI",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_PTELO, "PTELO",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_TLBMISS, "TLBMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
static void register_usprg3_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG3, "USPRG3",
@@ -9238,7 +9213,6 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 17607adbe411..f1da0e119d6f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -714,35 +714,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
break;
- case POWERPC_EXCP_74xx:
-#if defined(DEBUG_SOFTWARE_TLB)
- if (qemu_log_enabled()) {
- const char *es;
- target_ulong *miss, *cmp;
- int en;
-
- if (excp == POWERPC_EXCP_IFTLB) {
- es = "I";
- en = 'I';
- miss = &env->spr[SPR_TLBMISS];
- cmp = &env->spr[SPR_PTEHI];
- } else {
- if (excp == POWERPC_EXCP_DLTLB) {
- es = "DL";
- } else {
- es = "DS";
- }
- en = 'D';
- miss = &env->spr[SPR_TLBMISS];
- cmp = &env->spr[SPR_PTEHI];
- }
- qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
- TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
- env->error_code);
- }
-#endif
- msr |= env->error_code; /* key bit */
- break;
default:
cpu_abort(cs, "Invalid TLB miss exception\n");
break;
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 754509e556c0..86795b281427 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1147,7 +1147,6 @@ void dump_mmu(CPUPPCState *env)
mmubooke206_dump_mmu(env);
break;
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
mmu6xx_dump_mmu(env);
break;
#if defined(TARGET_PPC64)
@@ -1181,7 +1180,6 @@ static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
ret = 0;
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_REAL:
case POWERPC_MMU_BOOKE:
@@ -1234,7 +1232,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
} else {
@@ -1383,9 +1380,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_IMISS] = eaddr;
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
- case POWERPC_MMU_SOFT_74xx:
- cs->exception_index = POWERPC_EXCP_IFTLB;
- goto tlb_miss_74xx;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_ITLB;
@@ -1454,19 +1448,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) +
get_pteg_offset32(cpu, ctx.hash[1]);
break;
- case POWERPC_MMU_SOFT_74xx:
- if (access_type == MMU_DATA_STORE) {
- cs->exception_index = POWERPC_EXCP_DSTLB;
- } else {
- cs->exception_index = POWERPC_EXCP_DLTLB;
- }
- tlb_miss_74xx:
- /* Implement LRU algorithm */
- env->error_code = ctx.key << 19;
- env->spr[SPR_TLBMISS] = (eaddr & ~((target_ulong)0x3)) |
- ((env->last_way + 1) & (env->nb_ways - 1));
- env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
- break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_DTLB;
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index e0c4950dda53..f992131c1aa5 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -385,7 +385,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
#endif /* defined(TARGET_PPC64) */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
ppc6xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_SOFT_4xx:
@@ -434,7 +433,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
#endif /* defined(TARGET_PPC64) */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
ppc6xx_tlb_invalidate_virt(env, addr, 0);
if (env->id_tlbs == 1) {
ppc6xx_tlb_invalidate_virt(env, addr, 1);
@@ -571,35 +569,6 @@ void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN)
do_6xx_tlb(env, EPN, 1);
}
-/* PowerPC 74xx software TLB load instructions helpers */
-static void do_74xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
-{
- target_ulong RPN, CMP, EPN;
- int way;
-
- RPN = env->spr[SPR_PTELO];
- CMP = env->spr[SPR_PTEHI];
- EPN = env->spr[SPR_TLBMISS] & ~0x3;
- way = env->spr[SPR_TLBMISS] & 0x3;
- (void)EPN; /* avoid a compiler warning */
- LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
- " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
- RPN, way);
- /* Store this TLB */
- ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
- way, is_code, CMP, RPN);
-}
-
-void helper_74xx_tlbd(CPUPPCState *env, target_ulong EPN)
-{
- do_74xx_tlb(env, EPN, 0);
-}
-
-void helper_74xx_tlbi(CPUPPCState *env, target_ulong EPN)
-{
- do_74xx_tlb(env, EPN, 1);
-}
-
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9960df6e1839..b3f3b408db18 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6252,30 +6252,6 @@ static void gen_tlbli_6xx(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* 74xx TLB management */
-
-/* tlbld */
-static void gen_tlbld_74xx(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
- gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* tlbli */
-static void gen_tlbli_74xx(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
- gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* POWER instructions not in PowerPC 601 */
/* clf */
@@ -7735,8 +7711,6 @@ GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
-GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
-GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 057/102] target/ppc: Fix MPCxxx FPU interrupt address
2021-12-15 17:02 ` Cédric Le Goater
` (42 preceding siblings ...)
2021-12-15 17:03 ` [PULL 056/102] target/ppc: Remove the software TLB model of 7450 CPUs Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 058/102] target/ppc: Remove 603e exception model Cédric Le Goater
` (44 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ed0e2136d9c8..7e61994e3596 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2155,7 +2155,7 @@ static void init_excp_MPC5xx(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
@@ -2182,7 +2182,7 @@ static void init_excp_MPC8xx(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 058/102] target/ppc: Remove 603e exception model
2021-12-15 17:02 ` Cédric Le Goater
` (43 preceding siblings ...)
2021-12-15 17:03 ` [PULL 057/102] target/ppc: Fix MPCxxx FPU interrupt address Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 059/102] target/ppc: Set 601v exception model id Cédric Le Goater
` (43 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu-qom.h | 2 --
target/ppc/cpu_init.c | 32 ++------------------------------
target/ppc/excp_helper.c | 1 -
3 files changed, 2 insertions(+), 33 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index ef9e32447473..7d299f90c74f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -98,8 +98,6 @@ enum powerpc_excp_t {
POWERPC_EXCP_602,
/* PowerPC 603 exception model */
POWERPC_EXCP_603,
- /* PowerPC 603e exception model */
- POWERPC_EXCP_603E,
/* PowerPC G2 exception model */
POWERPC_EXCP_G2,
/* PowerPC 604 exception model */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7e61994e3596..db065687775d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4721,41 +4721,13 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_603E(CPUPPCState *env)
-{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_603_sprs(env);
- /* Time base */
- register_tbl(env);
- /* hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
- register_low_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->desc = "PowerPC 603e";
- pcc->init_proc = init_proc_603E;
+ pcc->init_proc = init_proc_603;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
@@ -4781,7 +4753,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603E;
+ pcc->excp_model = POWERPC_EXCP_603;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_ec603e;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f1da0e119d6f..1612b9b30e35 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -672,7 +672,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
switch (excp_model) {
case POWERPC_EXCP_602:
case POWERPC_EXCP_603:
- case POWERPC_EXCP_603E:
case POWERPC_EXCP_G2:
/* Swap temporary saved registers with GPRs */
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 059/102] target/ppc: Set 601v exception model id
2021-12-15 17:02 ` Cédric Le Goater
` (44 preceding siblings ...)
2021-12-15 17:03 ` [PULL 058/102] target/ppc: Remove 603e exception model Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 060/102] target/ppc: remove 401/403 CPUs Cédric Le Goater
` (42 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index db065687775d..ccdd5c9bad01 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4579,6 +4579,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
(1ull << MSR_IR) |
(1ull << MSR_DR);
pcc->mmu_model = POWERPC_MMU_601;
+ pcc->excp_model = POWERPC_EXCP_601;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_601;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 060/102] target/ppc: remove 401/403 CPUs
2021-12-15 17:02 ` Cédric Le Goater
` (45 preceding siblings ...)
2021-12-15 17:03 ` [PULL 059/102] target/ppc: Set 601v exception model id Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 061/102] ppc/ppc405: Change kernel load address Cédric Le Goater
` (41 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211202191108.1291515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu-models.h | 19 --
target/ppc/cpu-qom.h | 4 -
target/ppc/cpu-models.c | 34 ---
target/ppc/cpu_init.c | 512 ---------------------------------------
target/ppc/excp_helper.c | 1 -
target/ppc/mmu_common.c | 41 +---
target/ppc/mmu_helper.c | 1 -
7 files changed, 4 insertions(+), 608 deletions(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 095259275941..bf1dc7e5ca3d 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -38,27 +38,8 @@ extern PowerPCCPUAlias ppc_cpu_aliases[];
/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
- /* PowerPC 401 family */
- /* Generic PowerPC 401 */
-#define CPU_POWERPC_401 CPU_POWERPC_401G2
- /* PowerPC 401 cores */
- CPU_POWERPC_401A1 = 0x00210000,
- CPU_POWERPC_401B2 = 0x00220000,
- CPU_POWERPC_401C2 = 0x00230000,
- CPU_POWERPC_401D2 = 0x00240000,
- CPU_POWERPC_401E2 = 0x00250000,
- CPU_POWERPC_401F2 = 0x00260000,
- CPU_POWERPC_401G2 = 0x00270000,
- /* PowerPC 401 microcontrolers */
-#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
/* IBM Processor for Network Resources */
CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
- /* PowerPC 403 family */
- /* PowerPC 403 microcontrollers */
- CPU_POWERPC_403GA = 0x00200011,
- CPU_POWERPC_403GB = 0x00200100,
- CPU_POWERPC_403GC = 0x00200200,
- CPU_POWERPC_403GCX = 0x00201400,
/* PowerPC 405 family */
/* PowerPC 405 cores */
CPU_POWERPC_405D2 = 0x20010000,
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 7d299f90c74f..99a6b509af08 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -53,8 +53,6 @@ enum powerpc_mmu_t {
POWERPC_MMU_SOFT_74xx = 0x00000003,
/* PowerPC 4xx MMU with software TLB */
POWERPC_MMU_SOFT_4xx = 0x00000004,
- /* PowerPC 4xx MMU with software TLB and zones protections */
- POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
/* PowerPC MMU in real mode only */
POWERPC_MMU_REAL = 0x00000006,
/* Freescale MPC8xx MMU model */
@@ -149,8 +147,6 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_POWER7,
/* PowerPC POWER9 bus */
PPC_FLAGS_INPUT_POWER9,
- /* PowerPC 401 bus */
- PPC_FLAGS_INPUT_401,
/* Freescale RCPU bus */
PPC_FLAGS_INPUT_RCPU,
};
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 4baa111713b0..c9fcb6119f40 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -67,40 +67,6 @@
POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type)
/* Embedded PowerPC */
- /* PowerPC 401 family */
- POWERPC_DEF("401", CPU_POWERPC_401, 401,
- "Generic PowerPC 401")
- /* PowerPC 401 cores */
- POWERPC_DEF("401a1", CPU_POWERPC_401A1, 401,
- "PowerPC 401A1")
- POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2,
- "PowerPC 401B2")
- POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2,
- "PowerPC 401C2")
- POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2,
- "PowerPC 401D2")
- POWERPC_DEF("401e2", CPU_POWERPC_401E2, 401x2,
- "PowerPC 401E2")
- POWERPC_DEF("401f2", CPU_POWERPC_401F2, 401x2,
- "PowerPC 401F2")
- /* XXX: to be checked */
- POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2,
- "PowerPC 401G2")
- /* PowerPC 401 microcontrollers */
- POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480,
- "IOP480 (401 microcontroller)")
- POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401,
- "IBM Processor for Network Resources")
- /* PowerPC 403 family */
- /* PowerPC 403 microcontrollers */
- POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403,
- "PowerPC 403 GA")
- POWERPC_DEF("403gb", CPU_POWERPC_403GB, 403,
- "PowerPC 403 GB")
- POWERPC_DEF("403gc", CPU_POWERPC_403GC, 403,
- "PowerPC 403 GC")
- POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX,
- "PowerPC 403 GCX")
/* PowerPC 405 family */
/* PowerPC 405 cores */
POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ccdd5c9bad01..96034889dd02 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1553,169 +1553,6 @@ static void register_405_sprs(CPUPPCState *env)
register_usprgh_sprs(env);
}
-/* SPR shared between PowerPC 401 & 403 implementations */
-static void register_401_403_sprs(CPUPPCState *env)
-{
- /* Time base */
- spr_register(env, SPR_403_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_403_TBL, "TBL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_403_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_403_TBU, "TBU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu,
- 0x00000000);
- /* Debug */
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_403_CDBCR, "CDBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 401 implementation */
-static void register_401_sprs(CPUPPCState *env)
-{
- /* Debug interface */
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBCR0, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC1, "DAC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC1, "IAC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Storage control */
- /* XXX: TODO: not implemented */
- spr_register(env, SPR_405_SLER, "SLER",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_sler,
- 0x00000000);
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void register_401x2_sprs(CPUPPCState *env)
-{
- register_401_sprs(env);
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC 403 implementation */
-static void register_403_sprs(CPUPPCState *env)
-{
- /* Debug interface */
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBCR0, "DBCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_40x_dbcr0,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DBSR, "DBSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- /* Last reset was system reset */
- 0x00000300);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC1, "DAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_DAC2, "DAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC1, "IAC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_40x_IAC2, "IAC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-static void register_403_real_sprs(CPUPPCState *env)
-{
- spr_register(env, SPR_403_PBL1, "PBL1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBU1, "PBU1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBL2, "PBL2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
- spr_register(env, SPR_403_PBU2, "PBU2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_403_pbr, &spr_write_403_pbr,
- 0x00000000);
-}
-
-static void register_403_mmu_sprs(CPUPPCState *env)
-{
- /* MMU */
- spr_register(env, SPR_40x_PID, "PID",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_40x_ZPR, "ZPR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
-/* SPR specific to PowerPC compression coprocessor extension */
-static void register_compress_sprs(CPUPPCState *env)
-{
- /* XXX : not implemented */
- spr_register(env, SPR_401_SKR, "SKR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
static void register_5xx_8xx_sprs(CPUPPCState *env)
{
@@ -2103,26 +1940,6 @@ static void register_8xx_sprs(CPUPPCState *env)
/*****************************************************************************/
/* Exception vectors models */
-static void init_excp_4xx_real(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
- env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
- env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
- env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
- env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
- env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
- env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
- env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
- env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
- env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->ivor_mask = 0x0000FFF0UL;
- env->ivpr_mask = 0xFFFF0000UL;
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
-}
-
static void init_excp_4xx_softmmu(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -2662,335 +2479,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
\
static void glue(glue(ppc_, _name), _cpu_family_class_init)
-static void init_proc_401(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_401_sprs(env);
- init_excp_4xx_real(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401";
- pcc->init_proc = init_proc_401;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_WRTEE | PPC_DCR |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_401x2(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_401x2_sprs(env);
- register_compress_sprs(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401x2";
- pcc->init_proc = init_proc_401x2;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_401x3(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_401_sprs(env);
- register_401x2_sprs(env);
- register_compress_sprs(env);
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 401x3";
- pcc->init_proc = init_proc_401x3;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_IOP480(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_401x2_sprs(env);
- register_compress_sprs(env);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "IOP480";
- pcc->init_proc = init_proc_IOP480;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << 20) |
- (1ull << MSR_KEY) |
- (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_DE) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_403(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_403_sprs(env);
- register_403_real_sprs(env);
- init_excp_4xx_real(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 403";
- pcc->init_proc = init_proc_403;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_PE) |
- (1ull << MSR_PX) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
- POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_403GCX(CPUPPCState *env)
-{
- register_40x_sprs(env);
- register_401_403_sprs(env);
- register_403_sprs(env);
- register_403_real_sprs(env);
- register_403_mmu_sprs(env);
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_4xx_softmmu(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc40x_irq_init(env_archcpu(env));
-
- SET_FIT_PERIOD(8, 12, 16, 20);
- SET_WDT_PERIOD(16, 20, 24, 28);
-}
-
-POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 403 GCX";
- pcc->init_proc = init_proc_403GCX;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_WRTEE |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
- PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
- PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_ME) |
- (1ull << MSR_PE) |
- (1ull << MSR_PX) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
- pcc->excp_model = POWERPC_EXCP_40x;
- pcc->bus_model = PPC_FLAGS_INPUT_401;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
- POWERPC_FLAG_BUS_CLK;
-}
-
static void init_proc_405(CPUPPCState *env)
{
/* Time base */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1612b9b30e35..cbd88f74c9df 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1434,7 +1434,6 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
env->spr[SPR_40x_DEAR] = vaddr;
break;
case POWERPC_MMU_BOOKE:
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 86795b281427..4e278365ca55 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -1173,11 +1173,9 @@ void dump_mmu(CPUPPCState *env)
static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
MMUAccessType access_type)
{
- int in_plb, ret;
-
ctx->raddr = eaddr;
ctx->prot = PAGE_READ | PAGE_EXEC;
- ret = 0;
+
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_4xx:
@@ -1186,39 +1184,12 @@ static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
ctx->prot |= PAGE_WRITE;
break;
- case POWERPC_MMU_SOFT_4xx_Z:
- if (unlikely(msr_pe != 0)) {
- /*
- * 403 family add some particular protections, using
- * PBL/PBU registers for accesses with no translation.
- */
- in_plb =
- /* Check PLB validity */
- (env->pb[0] < env->pb[1] &&
- /* and address in plb area */
- eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
- (env->pb[2] < env->pb[3] &&
- eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
- if (in_plb ^ msr_px) {
- /* Access in protected area */
- if (access_type == MMU_DATA_STORE) {
- /* Access is not allowed */
- ret = -2;
- }
- } else {
- /* Read-write access is allowed */
- ctx->prot |= PAGE_WRITE;
- }
- }
- break;
-
default:
/* Caller's checks mean we should never get here for other models */
- abort();
- return -1;
+ g_assert_not_reached();
}
- return ret;
+ return 0;
}
int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
@@ -1247,7 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
break;
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, access_type);
} else {
@@ -1381,7 +1351,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
@@ -1449,7 +1418,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
get_pteg_offset32(cpu, ctx.hash[1]);
break;
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = eaddr;
@@ -1482,8 +1450,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
- if (env->mmu_model == POWERPC_MMU_SOFT_4xx
- || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
+ if (env->mmu_model == POWERPC_MMU_SOFT_4xx) {
env->spr[SPR_40x_DEAR] = eaddr;
if (access_type == MMU_DATA_STORE) {
env->spr[SPR_40x_ESR] |= 0x00800000;
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f992131c1aa5..2ec3d203a081 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -388,7 +388,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
ppc6xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_SOFT_4xx:
- case POWERPC_MMU_SOFT_4xx_Z:
ppc4xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_REAL:
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 061/102] ppc/ppc405: Change kernel load address
2021-12-15 17:02 ` Cédric Le Goater
` (46 preceding siblings ...)
2021-12-15 17:03 ` [PULL 060/102] target/ppc: remove 401/403 CPUs Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 062/102] ppc: Mark the 'taihu' machine as deprecated Cédric Le Goater
` (40 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Christophe Leroy, Peter Maydell, Thomas Huth, Richard Henderson,
Cédric Le Goater
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=1000000\0"
"fdt_addr_r=1800000\0"
"ramdisk_addr_r=1900000\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.
Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.
Change the kernel load address to match U-Boot expectations and fix
loading.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 972a7a4a3e5d..b4249f4626e6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -45,7 +45,7 @@
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)
-#define KERNEL_LOAD_ADDR 0x00000000
+#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
#define USE_FLASH_BIOS
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 062/102] ppc: Mark the 'taihu' machine as deprecated
2021-12-15 17:02 ` Cédric Le Goater
` (47 preceding siblings ...)
2021-12-15 17:03 ` [PULL 061/102] ppc/ppc405: Change kernel load address Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 063/102] ppc: Add trace-events for DCR accesses Cédric Le Goater
` (39 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Thomas Huth, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
From: Thomas Huth <thuth@redhat.com>
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added by this board. The users
can use the 'ref405ep' machine to test their PPC405 code instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211203164904.290954-2-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/about/deprecated.rst | 9 +++++++++
hw/ppc/ppc405_boards.c | 1 +
2 files changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index ff7488cb63b9..5693abb663e3 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -315,6 +315,15 @@ This machine is deprecated because we have enough AST2500 based OpenPOWER
machines. It can be easily replaced by the ``witherspoon-bmc`` or the
``romulus-bmc`` machines.
+PPC 405 ``taihu`` machine (since 7.0)
+'''''''''''''''''''''''''''''''''''''
+
+The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
+except for some external periphery. However, the periphery of the ``taihu``
+machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
+been implemented), so there is not much value added by this board. Use the
+``ref405ep`` machine instead.
+
Backend options
---------------
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b4249f4626e6..f1623aa622a6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -547,6 +547,7 @@ static void taihu_class_init(ObjectClass *oc, void *data)
mc->init = taihu_405ep_init;
mc->default_ram_size = 0x08000000;
mc->default_ram_id = "taihu_405ep.ram";
+ mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
}
static const TypeInfo taihu_type = {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 063/102] ppc: Add trace-events for DCR accesses
2021-12-15 17:02 ` Cédric Le Goater
` (48 preceding siblings ...)
2021-12-15 17:03 ` [PULL 062/102] ppc: Mark the 'taihu' machine as deprecated Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 064/102] ppc/ppc405: Convert printfs to trace-events Cédric Le Goater
` (38 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc.c | 2 ++
hw/ppc/trace-events | 3 +++
2 files changed, 5 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index e8127599c907..818d75798584 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1367,6 +1367,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
if (dcr->dcr_read == NULL)
goto error;
*valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
+ trace_ppc_dcr_read(dcrn, *valp);
return 0;
@@ -1386,6 +1387,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
dcr = &dcr_env->dcrn[dcrn];
if (dcr->dcr_write == NULL)
goto error;
+ trace_ppc_dcr_write(dcrn, val);
(*dcr->dcr_write)(dcr->opaque, dcrn, val);
return 0;
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 3bf43fa340fe..602adb83157b 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -119,6 +119,9 @@ ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d"
ppc_irq_reset(const char *name) "%s"
ppc_irq_cpu(const char *action) "%s"
+ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x"
+ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x"
+
# prep_systemio.c
prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 064/102] ppc/ppc405: Convert printfs to trace-events
2021-12-15 17:02 ` Cédric Le Goater
` (49 preceding siblings ...)
2021-12-15 17:03 ` [PULL 063/102] ppc: Add trace-events for DCR accesses Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 065/102] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() Cédric Le Goater
` (37 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_uc.c | 159 +++++++++++++++-----------------------------
hw/ppc/trace-events | 20 ++++++
2 files changed, 74 insertions(+), 105 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e632c408bdf8..e14d61e9b899 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
@@ -38,15 +39,7 @@
#include "hw/intc/ppc-uic.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
-
-//#define DEBUG_OPBA
-//#define DEBUG_SDRAM
-//#define DEBUG_GPIO
-//#define DEBUG_SERIAL
-//#define DEBUG_OCM
-//#define DEBUG_GPT
-//#define DEBUG_CLOCKS
-//#define DEBUG_CLOCKS_LL
+#include "trace.h"
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
@@ -287,13 +280,9 @@ struct ppc4xx_opba_t {
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_opba_t *opba;
+ ppc4xx_opba_t *opba = opaque;
uint32_t ret;
-#ifdef DEBUG_OPBA
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- opba = opaque;
switch (addr) {
case 0x00:
ret = opba->cr;
@@ -306,19 +295,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
break;
}
+ trace_opba_readb(addr, ret);
return ret;
}
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_opba_t *opba;
+ ppc4xx_opba_t *opba = opaque;
+
+ trace_opba_writeb(addr, value);
-#ifdef DEBUG_OPBA
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- opba = opaque;
switch (addr) {
case 0x00:
opba->cr = value & 0xF8;
@@ -353,10 +340,9 @@ static void ppc4xx_opba_init(hwaddr base)
{
ppc4xx_opba_t *opba;
+ trace_opba_init(base);
+
opba = g_malloc0(sizeof(ppc4xx_opba_t));
-#ifdef DEBUG_OPBA
- printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
@@ -707,20 +693,14 @@ struct ppc405_gpio_t {
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
-#ifdef DEBUG_GPIO
- printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);
-#endif
-
+ trace_ppc405_gpio_read(addr, size);
return 0;
}
static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
-#ifdef DEBUG_GPIO
- printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",
- __func__, addr, size, value);
-#endif
+ trace_ppc405_gpio_write(addr, size, value);
}
static const MemoryRegionOps ppc405_gpio_ops = {
@@ -737,10 +717,9 @@ static void ppc405_gpio_init(hwaddr base)
{
ppc405_gpio_t *gpio;
+ trace_ppc405_gpio_init(base);
+
gpio = g_malloc0(sizeof(ppc405_gpio_t));
-#ifdef DEBUG_GPIO
- printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
@@ -770,25 +749,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
{
-#ifdef DEBUG_OCM
- printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
- " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
- " (%08" PRIx32 " %08" PRIx32 ")\n",
- isarc, isacntl, dsarc, dsacntl,
- ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
-#endif
+ trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
+ ocm->isacntl, ocm->dsarc, ocm->dsacntl);
+
if (ocm->isarc != isarc ||
(ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
- printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
+ trace_ocm_unmap("ISA", ocm->isarc);
memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
-#ifdef DEBUG_OCM
- printf("OCM map ISA %08" PRIx32 "\n", isarc);
-#endif
+ trace_ocm_map("ISA", isarc);
memory_region_add_subregion(get_system_memory(), isarc,
&ocm->isarc_ram);
}
@@ -799,9 +772,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
/* Beware not to unmap the region we just mapped */
if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
/* Unmap previously assigned memory region */
-#ifdef DEBUG_OCM
- printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
-#endif
+ trace_ocm_unmap("DSA", ocm->dsarc);
memory_region_del_subregion(get_system_memory(),
&ocm->dsarc_ram);
}
@@ -810,9 +781,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
/* Beware not to remap the region we just mapped */
if (!(isacntl & 0x80000000) || dsarc != isarc) {
/* Map new data memory region */
-#ifdef DEBUG_OCM
- printf("OCM map DSA %08" PRIx32 "\n", dsarc);
-#endif
+ trace_ocm_map("DSA", dsarc);
memory_region_add_subregion(get_system_memory(), dsarc,
&ocm->dsarc_ram);
}
@@ -988,14 +957,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_gpt_t *gpt;
+ ppc4xx_gpt_t *gpt = opaque;
uint32_t ret;
int idx;
-#ifdef DEBUG_GPT
- printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
- gpt = opaque;
+ trace_ppc4xx_gpt_read(addr, size);
+
switch (addr) {
case 0x00:
/* Time base counter */
@@ -1044,14 +1011,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_gpt_t *gpt;
+ ppc4xx_gpt_t *gpt = opaque;
int idx;
-#ifdef DEBUG_I2C
- printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
- value);
-#endif
- gpt = opaque;
+ trace_ppc4xx_gpt_write(addr, size, value);
+
switch (addr) {
case 0x00:
/* Time base counter */
@@ -1144,14 +1108,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
ppc4xx_gpt_t *gpt;
int i;
+ trace_ppc4xx_gpt_init(base);
+
gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
-#ifdef DEBUG_GPT
- printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
@@ -1215,17 +1178,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
VCO_out = 0;
if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
-#ifdef DEBUG_CLOCKS_LL
- printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
-#endif
+ trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
-#ifdef DEBUG_CLOCKS_LL
- printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
-#endif
+ trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
VCO_out = (uint64_t)cpc->sysclk * M * D;
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
/* Error - unlock the PLL */
- printf("VCO out of range %" PRIu64 "\n", VCO_out);
+ qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
+ VCO_out);
#if 0
cpc->pllmr[1] &= ~0x80000000;
goto pll_bypass;
@@ -1246,54 +1206,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
}
/* Now, compute all other clocks */
D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
CPU_clk = PLL_out / D;
D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
PLB_clk = CPU_clk / D;
D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
OPB_clk = PLB_clk / D;
D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
EBC_clk = PLB_clk / D;
D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
MAL_clk = PLB_clk / D;
D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
-#ifdef DEBUG_CLOCKS_LL
- printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
-#endif
+ trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
PCI_clk = PLB_clk / D;
D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
-#ifdef DEBUG_CLOCKS_LL
- printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
-#endif
+ trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
UART0_clk = PLL_out / D;
D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
-#ifdef DEBUG_CLOCKS_LL
- printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
-#endif
+ trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
UART1_clk = PLL_out / D;
-#ifdef DEBUG_CLOCKS
- printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
- " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
- printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
- " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
- " UART1 %" PRIu32 "\n",
- CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
- UART0_clk, UART1_clk);
-#endif
+
+ if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
+ g_autofree char *trace = g_strdup_printf(
+ "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
+ " PLL out %" PRIu64 " Hz\n"
+ "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
+ " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
+ " UART1 %" PRIu32 "\n",
+ cpc->sysclk, VCO_out, PLL_out,
+ CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
+ UART0_clk, UART1_clk);
+ trace_ppc405ep_clocks_setup(trace);
+ }
+
/* Setup CPU clocks */
clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
/* Setup PLB clock */
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 602adb83157b..ada644652d94 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -144,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of
ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64
ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32
+
+# ppc405_boards.c
+opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
+opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
+opba_init(uint64_t addr) "offet 0x%" PRIx64
+
+ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
+ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
+ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64
+
+ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")"
+ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32
+ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
+
+ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
+ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
+ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64
+
+ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d"
+ppc405ep_clocks_setup(const char *trace) "%s"
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 065/102] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()
2021-12-15 17:02 ` Cédric Le Goater
` (50 preceding siblings ...)
2021-12-15 17:03 ` [PULL 064/102] ppc/ppc405: Convert printfs to trace-events Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 066/102] ppc/ppc405: Change ppc405ep_init() return value Cédric Le Goater
` (36 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Philippe Mathieu-Daudé
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 3 +--
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 8 +++-----
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c58f739886a6..4cb77aca5690 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -56,8 +56,7 @@ struct ppc4xx_bd_info_t {
};
/* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
- uint32_t flags);
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index f1623aa622a6..2ac38c86a643 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -261,7 +261,7 @@ static void ref405ep_init(MachineState *machine)
bd.bi_plb_busfreq = 33333333;
bd.bi_pci_busfreq = 33333333;
bd.bi_opbfreq = 33333333;
- bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
+ bdloc = ppc405_set_bootinfo(env, &bd);
env->gpr[3] = bdloc;
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e14d61e9b899..6806d6be31d5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -41,8 +41,7 @@
#include "qapi/error.h"
#include "trace.h"
-ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
- uint32_t flags)
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
{
CPUState *cs = env_cpu(env);
ram_addr_t bdloc;
@@ -81,9 +80,8 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
}
n = 0x6A;
- if (flags & 0x00000001) {
- for (i = 0; i < 6; i++)
- stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
+ for (i = 0; i < 6; i++) {
+ stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
n += 4;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 066/102] ppc/ppc405: Change ppc405ep_init() return value
2021-12-15 17:02 ` Cédric Le Goater
` (51 preceding siblings ...)
2021-12-15 17:03 ` [PULL 065/102] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 067/102] ppc/ppc405: Add some address space definitions Cédric Le Goater
` (35 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_boards.c | 6 +++++-
hw/ppc/ppc405_uc.c | 4 ++--
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4cb77aca5690..ad5f4026b5db 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -61,7 +61,7 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
-CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
+PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
hwaddr ram_bases[2],
hwaddr ram_sizes[2],
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 2ac38c86a643..fcdb6d4cf8a0 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -145,6 +145,7 @@ static void ref405ep_init(MachineState *machine)
const char *initrd_filename = machine->initrd_filename;
char *filename;
ppc4xx_bd_info_t bd;
+ PowerPCCPU *cpu;
CPUPPCState *env;
DeviceState *dev;
SysBusDevice *s;
@@ -180,8 +181,11 @@ static void ref405ep_init(MachineState *machine)
memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
- env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+
+ cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
+ env = &cpu->env;
+
/* allocate SRAM */
sram_size = 512 * KiB;
memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 6806d6be31d5..4ad81695e80a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1391,7 +1391,7 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
#endif
}
-CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
+PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
hwaddr ram_bases[2],
hwaddr ram_sizes[2],
@@ -1490,5 +1490,5 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
/* CPU control */
ppc405ep_cpc_init(env, clk_setup, sysclk);
- return env;
+ return cpu;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 067/102] ppc/ppc405: Add some address space definitions
2021-12-15 17:02 ` Cédric Le Goater
` (52 preceding siblings ...)
2021-12-15 17:03 ` [PULL 066/102] ppc/ppc405: Change ppc405ep_init() return value Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 068/102] ppc/ppc405: Remove flash support Cédric Le Goater
` (34 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 7 +++++++
hw/ppc/ppc405_boards.c | 16 +++++++---------
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad5f4026b5db..ea48c3626908 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,13 @@
#include "hw/ppc/ppc4xx.h"
+#define PPC405EP_SDRAM_BASE 0x00000000
+#define PPC405EP_NVRAM_BASE 0xF0000000
+#define PPC405EP_FPGA_BASE 0xF0300000
+#define PPC405EP_SRAM_BASE 0xFFF00000
+#define PPC405EP_SRAM_SIZE (512 * KiB)
+#define PPC405EP_FLASH_BASE 0xFFF80000
+
/* Bootinfo as set-up by u-boot */
typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
struct ppc4xx_bd_info_t {
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index fcdb6d4cf8a0..60dc81fa4880 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine)
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
- target_ulong sram_size;
long bios_size;
//int phy_addr = 0;
//static int phy_addr = 1;
@@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine)
env = &cpu->env;
/* allocate SRAM */
- sram_size = 512 * KiB;
- memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
+ memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
&error_fatal);
- memory_region_add_subregion(sysmem, 0xFFF00000, sram);
+ memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
/* allocate and load BIOS */
#ifdef USE_FLASH_BIOS
dinfo = drive_get(IF_PFLASH, 0, 0);
@@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine)
}
}
/* Register FPGA */
- ref405ep_fpga_init(sysmem, 0xF0300000);
+ ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, 0xF0000000);
+ sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
/* Load kernel */
linux_boot = (kernel_filename != NULL);
if (linux_boot) {
memset(&bd, 0, sizeof(bd));
- bd.bi_memstart = 0x00000000;
+ bd.bi_memstart = PPC405EP_SDRAM_BASE;
bd.bi_memsize = machine->ram_size;
bd.bi_flashstart = -bios_size;
bd.bi_flashsize = -bios_size;
bd.bi_flashoffset = 0;
- bd.bi_sramstart = 0xFFF00000;
- bd.bi_sramsize = sram_size;
+ bd.bi_sramstart = PPC405EP_SRAM_BASE;
+ bd.bi_sramsize = PPC405EP_SRAM_SIZE;
bd.bi_bootflags = 0;
bd.bi_intfreq = 133333333;
bd.bi_busfreq = 33333333;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 068/102] ppc/ppc405: Remove flash support
2021-12-15 17:02 ` Cédric Le Goater
` (53 preceding siblings ...)
2021-12-15 17:03 ` [PULL 067/102] ppc/ppc405: Add some address space definitions Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 069/102] ppc/ppc405: Rework FW load Cédric Le Goater
` (33 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for about 10 years.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 60dc81fa4880..a385e8f15070 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -161,7 +161,6 @@ static void ref405ep_init(MachineState *machine)
long kernel_size, initrd_size;
int linux_boot;
int len;
- DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -189,19 +188,8 @@ static void ref405ep_init(MachineState *machine)
memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
&error_fatal);
memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
+
/* allocate and load BIOS */
-#ifdef USE_FLASH_BIOS
- dinfo = drive_get(IF_PFLASH, 0, 0);
- if (dinfo) {
- bios_size = 8 * MiB;
- pflash_cfi02_register((uint32_t)(-bios_size),
- "ef405ep.bios", bios_size,
- blk_by_legacy_dinfo(dinfo),
- 64 * KiB, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
- } else
-#endif
{
bios = g_new(MemoryRegion, 1);
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 069/102] ppc/ppc405: Rework FW load
2021-12-15 17:02 ` Cédric Le Goater
` (54 preceding siblings ...)
2021-12-15 17:03 ` [PULL 068/102] ppc/ppc405: Remove flash support Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 070/102] ppc/ppc405: Introduce ppc405_set_default_bootinfo() Cédric Le Goater
` (32 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffffffc where nothing is currently mapped. Support must
have been broken these last years.
Since we can not find a "ppc405_rom.bin" firmware file, request one to
be specified on the command line. A consequence of this change is that
the machine can be booted directly from Linux without any FW being
loaded. This is still broken and the CPU start address will be fixed
in the next changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 45 +++++++++++++++++++-----------------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index a385e8f15070..cfed43dba2f3 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -139,24 +139,19 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
static void ref405ep_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
- const char *bios_name = machine->firmware ?: BIOS_FILENAME;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
- char *filename;
ppc4xx_bd_info_t bd;
PowerPCCPU *cpu;
CPUPPCState *env;
DeviceState *dev;
SysBusDevice *s;
- MemoryRegion *bios;
MemoryRegion *sram = g_new(MemoryRegion, 1);
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
- long bios_size;
- //int phy_addr = 0;
- //static int phy_addr = 1;
+ long bios_size = -1;
target_ulong kernel_base, initrd_base;
long kernel_size, initrd_size;
int linux_boot;
@@ -190,31 +185,31 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
/* allocate and load BIOS */
- {
- bios = g_new(MemoryRegion, 1);
+ if (machine->firmware) {
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ g_autofree char *filename;
+
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- if (filename) {
- bios_size = load_image_size(filename,
- memory_region_get_ram_ptr(bios),
- BIOS_SIZE);
- g_free(filename);
- if (bios_size < 0) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
- exit(1);
- }
- bios_size = (bios_size + 0xfff) & ~0xfff;
- memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
- } else if (!qtest_enabled() || kernel_filename != NULL) {
- error_report("Could not load PowerPC BIOS '%s'", bios_name);
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
+ if (!filename) {
+ error_report("Could not find firmware '%s'", machine->firmware);
+ exit(1);
+ }
+
+ bios_size = load_image_size(filename,
+ memory_region_get_ram_ptr(bios),
+ BIOS_SIZE);
+ if (bios_size < 0) {
+ error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
exit(1);
- } else {
- /* Avoid an uninitialized variable warning */
- bios_size = -1;
}
+
+ bios_size = (bios_size + 0xfff) & ~0xfff;
+ memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
}
+
/* Register FPGA */
ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
/* Register NVRAM */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 070/102] ppc/ppc405: Introduce ppc405_set_default_bootinfo()
2021-12-15 17:02 ` Cédric Le Goater
` (55 preceding siblings ...)
2021-12-15 17:03 ` [PULL 069/102] ppc/ppc405: Rework FW load Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 071/102] ppc/ppc405: Fix boot from kernel Cédric Le Goater
` (31 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_boards.c | 28 +---------------------------
hw/ppc/ppc405_uc.c | 41 ++++++++++++++++++++++++++++++++++++++++-
3 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ea48c3626908..6fb8b41bbc77 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,7 +63,7 @@ struct ppc4xx_bd_info_t {
};
/* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index cfed43dba2f3..71a652e2d846 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -142,7 +142,6 @@ static void ref405ep_init(MachineState *machine)
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
- ppc4xx_bd_info_t bd;
PowerPCCPU *cpu;
CPUPPCState *env;
DeviceState *dev;
@@ -221,32 +220,7 @@ static void ref405ep_init(MachineState *machine)
/* Load kernel */
linux_boot = (kernel_filename != NULL);
if (linux_boot) {
- memset(&bd, 0, sizeof(bd));
- bd.bi_memstart = PPC405EP_SDRAM_BASE;
- bd.bi_memsize = machine->ram_size;
- bd.bi_flashstart = -bios_size;
- bd.bi_flashsize = -bios_size;
- bd.bi_flashoffset = 0;
- bd.bi_sramstart = PPC405EP_SRAM_BASE;
- bd.bi_sramsize = PPC405EP_SRAM_SIZE;
- bd.bi_bootflags = 0;
- bd.bi_intfreq = 133333333;
- bd.bi_busfreq = 33333333;
- bd.bi_baudrate = 115200;
- bd.bi_s_version[0] = 'Q';
- bd.bi_s_version[1] = 'M';
- bd.bi_s_version[2] = 'U';
- bd.bi_s_version[3] = '\0';
- bd.bi_r_version[0] = 'Q';
- bd.bi_r_version[1] = 'E';
- bd.bi_r_version[2] = 'M';
- bd.bi_r_version[3] = 'U';
- bd.bi_r_version[4] = '\0';
- bd.bi_procfreq = 133333333;
- bd.bi_plb_busfreq = 33333333;
- bd.bi_pci_busfreq = 33333333;
- bd.bi_opbfreq = 33333333;
- bdloc = ppc405_set_bootinfo(env, &bd);
+ bdloc = ppc405_set_bootinfo(env, machine->ram_size);
env->gpr[3] = bdloc;
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 4ad81695e80a..303af584443d 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -41,7 +41,35 @@
#include "qapi/error.h"
#include "trace.h"
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
+static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
+ ram_addr_t ram_size)
+{
+ memset(bd, 0, sizeof(*bd));
+
+ bd->bi_memstart = PPC405EP_SDRAM_BASE;
+ bd->bi_memsize = ram_size;
+ bd->bi_sramstart = PPC405EP_SRAM_BASE;
+ bd->bi_sramsize = PPC405EP_SRAM_SIZE;
+ bd->bi_bootflags = 0;
+ bd->bi_intfreq = 133333333;
+ bd->bi_busfreq = 33333333;
+ bd->bi_baudrate = 115200;
+ bd->bi_s_version[0] = 'Q';
+ bd->bi_s_version[1] = 'M';
+ bd->bi_s_version[2] = 'U';
+ bd->bi_s_version[3] = '\0';
+ bd->bi_r_version[0] = 'Q';
+ bd->bi_r_version[1] = 'E';
+ bd->bi_r_version[2] = 'M';
+ bd->bi_r_version[3] = 'U';
+ bd->bi_r_version[4] = '\0';
+ bd->bi_procfreq = 133333333;
+ bd->bi_plb_busfreq = 33333333;
+ bd->bi_pci_busfreq = 33333333;
+ bd->bi_opbfreq = 33333333;
+}
+
+static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
{
CPUState *cs = env_cpu(env);
ram_addr_t bdloc;
@@ -93,6 +121,17 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
return bdloc;
}
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
+{
+ ppc4xx_bd_info_t bd;
+
+ memset(&bd, 0, sizeof(bd));
+
+ ppc405_set_default_bootinfo(&bd, ram_size);
+
+ return __ppc405_set_bootinfo(env, &bd);
+}
+
/*****************************************************************************/
/* Shared peripherals */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 071/102] ppc/ppc405: Fix boot from kernel
2021-12-15 17:02 ` Cédric Le Goater
` (56 preceding siblings ...)
2021-12-15 17:03 ` [PULL 070/102] ppc/ppc405: Introduce ppc405_set_default_bootinfo() Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 072/102] ppc/ppc405: Change default PLL values at reset Cédric Le Goater
` (30 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset handler to setup the registers and to start the CPU
from the Linux kernel entry point.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 145 +++++++++++++++++++++++++++++------------
1 file changed, 102 insertions(+), 43 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 71a652e2d846..3ae2b36373a5 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -41,6 +41,7 @@
#include "qemu/error-report.h"
#include "hw/loader.h"
#include "qemu/cutils.h"
+#include "elf.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)
@@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
+/*
+ * CPU reset handler when booting directly from a loaded kernel
+ */
+static struct boot_info {
+ uint32_t entry;
+ uint32_t bdloc;
+ uint32_t initrd_base;
+ uint32_t initrd_size;
+ uint32_t cmdline_base;
+ uint32_t cmdline_size;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+ struct boot_info *bi = env->load_info;
+
+ cpu_reset(CPU(cpu));
+
+ /* stack: top of sram */
+ env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
+
+ /* Tune our boot state */
+ env->gpr[3] = bi->bdloc;
+ env->gpr[4] = bi->initrd_base;
+ env->gpr[5] = bi->initrd_base + bi->initrd_size;
+ env->gpr[6] = bi->cmdline_base;
+ env->gpr[7] = bi->cmdline_size;
+
+ env->nip = bi->entry;
+}
+
+static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ hwaddr boot_entry;
+ hwaddr kernel_base;
+ int kernel_size;
+ hwaddr initrd_base;
+ int initrd_size;
+ ram_addr_t bdloc;
+ int len;
+
+ bdloc = ppc405_set_bootinfo(env, machine->ram_size);
+ boot_info.bdloc = bdloc;
+
+ kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
+ &boot_entry, &kernel_base, NULL, NULL,
+ 1, PPC_ELF_MACHINE, 0, 0);
+ if (kernel_size < 0) {
+ error_report("Could not load kernel '%s' : %s",
+ machine->kernel_filename, load_elf_strerror(kernel_size));
+ exit(1);
+ }
+ boot_info.entry = boot_entry;
+
+ /* load initrd */
+ if (machine->initrd_filename) {
+ initrd_base = INITRD_LOAD_ADDR;
+ initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
+ machine->ram_size - initrd_base);
+ if (initrd_size < 0) {
+ error_report("could not load initial ram disk '%s'",
+ machine->initrd_filename);
+ exit(1);
+ }
+
+ boot_info.initrd_base = initrd_base;
+ boot_info.initrd_size = initrd_size;
+ }
+
+ if (machine->kernel_cmdline) {
+ len = strlen(machine->kernel_cmdline);
+ bdloc -= ((len + 255) & ~255);
+ cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
+ boot_info.cmdline_base = bdloc;
+ boot_info.cmdline_size = bdloc + len;
+ }
+
+ /* Install our custom reset handler to start from Linux */
+ qemu_register_reset(main_cpu_reset, cpu);
+ env->load_info = &boot_info;
+}
+
static void ref405ep_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
PowerPCCPU *cpu;
- CPUPPCState *env;
DeviceState *dev;
SysBusDevice *s;
MemoryRegion *sram = g_new(MemoryRegion, 1);
- ram_addr_t bdloc;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
hwaddr ram_bases[2], ram_sizes[2];
- long bios_size = -1;
- target_ulong kernel_base, initrd_base;
- long kernel_size, initrd_size;
- int linux_boot;
- int len;
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine)
cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- env = &cpu->env;
/* allocate SRAM */
memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
@@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine)
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
g_autofree char *filename;
+ long bios_size;
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
@@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine)
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
- /* Load kernel */
- linux_boot = (kernel_filename != NULL);
- if (linux_boot) {
- bdloc = ppc405_set_bootinfo(env, machine->ram_size);
- env->gpr[3] = bdloc;
+
+ /* Load kernel and initrd using U-Boot images */
+ if (kernel_filename && machine->firmware) {
+ target_ulong kernel_base, initrd_base;
+ long kernel_size, initrd_size;
+
kernel_base = KERNEL_LOAD_ADDR;
- /* now we can load the kernel */
kernel_size = load_image_targphys(kernel_filename, kernel_base,
machine->ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
- printf("Load kernel size %ld at " TARGET_FMT_lx,
- kernel_size, kernel_base);
+
/* load initrd */
- if (initrd_filename) {
+ if (machine->initrd_filename) {
initrd_base = INITRD_LOAD_ADDR;
- initrd_size = load_image_targphys(initrd_filename, initrd_base,
+ initrd_size = load_image_targphys(machine->initrd_filename,
+ initrd_base,
machine->ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
- initrd_filename);
+ machine->initrd_filename);
exit(1);
}
- } else {
- initrd_base = 0;
- initrd_size = 0;
- }
- env->gpr[4] = initrd_base;
- env->gpr[5] = initrd_size;
- if (kernel_cmdline != NULL) {
- len = strlen(kernel_cmdline);
- bdloc -= ((len + 255) & ~255);
- cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
- env->gpr[6] = bdloc;
- env->gpr[7] = bdloc + len;
- } else {
- env->gpr[6] = 0;
- env->gpr[7] = 0;
}
- env->nip = KERNEL_LOAD_ADDR;
- } else {
- kernel_base = 0;
- kernel_size = 0;
- initrd_base = 0;
- initrd_size = 0;
- bdloc = 0;
+
+ /* Load ELF kernel and rootfs.cpio */
+ } else if (kernel_filename && !machine->firmware) {
+ boot_from_kernel(machine, cpu);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 072/102] ppc/ppc405: Change default PLL values at reset
2021-12-15 17:02 ` Cédric Le Goater
` (57 preceding siblings ...)
2021-12-15 17:03 ` [PULL 071/102] ppc/ppc405: Fix boot from kernel Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 073/102] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information Cédric Le Goater
` (29 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_uc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 303af584443d..2a1e2d71b08b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1381,9 +1381,9 @@ static void ppc405ep_cpc_reset (void *opaque)
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
- cpc->pllmr[0] = 0x00011010;
- cpc->pllmr[1] = 0x40000000;
- cpc->ucr = 0x00000000;
+ cpc->pllmr[0] = 0x00021002;
+ cpc->pllmr[1] = 0x80a552be;
+ cpc->ucr = 0x00004646;
cpc->srr = 0x00040000;
cpc->pci = 0x00000000;
cpc->er = 0x00000000;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 073/102] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information
2021-12-15 17:02 ` Cédric Le Goater
` (58 preceding siblings ...)
2021-12-15 17:03 ` [PULL 072/102] ppc/ppc405: Change default PLL values at reset Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 074/102] ppc/ppc405: Add update of bi_procfreq field Cédric Le Goater
` (28 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Philippe Mathieu-Daudé
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 6fb8b41bbc77..83f156f585c8 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -57,7 +57,7 @@ struct ppc4xx_bd_info_t {
uint32_t bi_plb_busfreq;
uint32_t bi_pci_busfreq;
uint8_t bi_pci_enetaddr[6];
- uint32_t bi_pci_enetaddr2[6];
+ uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
uint32_t bi_opbfreq;
uint32_t bi_iic_fast[2];
};
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 074/102] ppc/ppc405: Add update of bi_procfreq field
2021-12-15 17:02 ` Cédric Le Goater
` (59 preceding siblings ...)
2021-12-15 17:03 ` [PULL 073/102] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 075/102] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Cédric Le Goater
` (27 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_uc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2a1e2d71b08b..ec97b22bd019 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -102,12 +102,13 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
for (i = 0; i < 32; i++) {
stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
}
- stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
- stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
+ stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+ stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
}
- n = 0x6A;
+ n = 0x70; /* includes 2 bytes hole */
for (i = 0; i < 6; i++) {
stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 075/102] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
2021-12-15 17:02 ` Cédric Le Goater
` (60 preceding siblings ...)
2021-12-15 17:03 ` [PULL 074/102] ppc/ppc405: Add update of bi_procfreq field Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 076/102] target/ppc: Move xs{max,min}[cj]dp to decodetree Cédric Le Goater
` (26 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Victor Colombo, Peter Maydell, Richard Henderson,
Cédric Le Goater
From: Victor Colombo <victor.colombo@eldorado.org.br>
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by changing these instructions to use
GEN_VSX_HELPER_X3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 8 ++++----
target/ppc/fpu_helper.c | 4 ++--
target/ppc/translate/vsx-impl.c.inc | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 72b2c70ac1fc..fb946dc97420 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -403,10 +403,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)
-DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr)
+DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr)
DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 1e9a16154036..d144f21dc04f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2495,7 +2495,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
#define VSX_MAX_MINC(name, max) \
-void helper_##name(CPUPPCState *env, uint32_t opcode, \
+void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = *xt; \
@@ -2530,7 +2530,7 @@ VSX_MAX_MINC(xsmaxcdp, 1);
VSX_MAX_MINC(xsmincdp, 0);
#define VSX_MAX_MINJ(name, max) \
-void helper_##name(CPUPPCState *env, uint32_t opcode, \
+void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = *xt; \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index c0e38060b455..02df75339ed2 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 076/102] target/ppc: Move xs{max,min}[cj]dp to decodetree
2021-12-15 17:02 ` Cédric Le Goater
` (61 preceding siblings ...)
2021-12-15 17:03 ` [PULL 075/102] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 077/102] target/ppc: fix xscvqpdp register access Cédric Le Goater
` (25 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Victor Colombo, Peter Maydell, Richard Henderson,
Cédric Le Goater
From: Victor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 17 +++++++++++++---
target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++----
target/ppc/translate/vsx-ops.c.inc | 4 ----
3 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f68931f4f374..97b2476ce61b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -130,10 +130,14 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+%xx_xt 0:1 21:5
+%xx_xb 1:1 11:5
+%xx_xa 2:1 16:5
&XX2 xt xb uim:uint8_t
-%xx2_xt 0:1 21:5
-%xx2_xb 1:1 11:5
-@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
+@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
+
+&XX3 xt xa xb
+@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -455,3 +459,10 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
+
+## VSX Comparison Instructions
+
+XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
+XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
+XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
+XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 02df75339ed2..e2447750ddec 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1098,10 +1098,6 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
@@ -2185,6 +2181,32 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16)
TRANS(XXBLENDVW, do_xxblendv, MO_32)
TRANS(XXBLENDVD, do_xxblendv, MO_64)
+static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr xt, xa, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+
+ helper(cpu_env, xt, xa, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp)
+TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
+TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
+TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 152d1e5c3bfb..f980bc1bae47 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -207,10 +207,6 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
-GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
-GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
-GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
-GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 077/102] target/ppc: fix xscvqpdp register access
2021-12-15 17:02 ` Cédric Le Goater
` (62 preceding siblings ...)
2021-12-15 17:03 ` [PULL 076/102] target/ppc: Move xs{max,min}[cj]dp to decodetree Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 078/102] target/ppc: move xscvqpdp to decodetree Cédric Le Goater
` (24 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/translate/vsx-impl.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index e2447750ddec..ab5cb21f13a1 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -913,8 +913,9 @@ static void gen_xscvqpdp(DisasContext *ctx)
return;
}
opc = tcg_const_i32(ctx->opcode);
- xt = gen_vsr_ptr(xT(ctx->opcode));
- xb = gen_vsr_ptr(xB(ctx->opcode));
+
+ xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
tcg_temp_free_i32(opc);
tcg_temp_free_ptr(xt);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 078/102] target/ppc: move xscvqpdp to decodetree
2021-12-15 17:02 ` Cédric Le Goater
` (63 preceding siblings ...)
2021-12-15 17:03 ` [PULL 077/102] target/ppc: fix xscvqpdp register access Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 079/102] target/ppc: Fix e6500 boot Cédric Le Goater
` (23 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 4 ++++
target/ppc/fpu_helper.c | 10 +++-------
target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
target/ppc/translate/vsx-ops.c.inc | 1 -
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fb946dc97420..d166323b641c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -411,7 +411,7 @@ DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
-DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr)
+DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 97b2476ce61b..8bdc059a4c79 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -466,3 +466,7 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
+
+## VSX Binary Floating-Point Convert Instructions
+
+XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d144f21dc04f..700c79156b06 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2751,18 +2751,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
-/*
- * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
- * added to this later.
- */
-void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
- ppc_vsr_t *xt, ppc_vsr_t *xb)
+void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
+ ppc_vsr_t *xb)
{
ppc_vsr_t t = { };
float_status tstat;
tstat = env->fp_status;
- if (unlikely(Rc(opcode) != 0)) {
+ if (ro != 0) {
tstat.float_rounding_mode = float_round_to_odd;
}
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ab5cb21f13a1..c08185e857e9 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
-static void gen_xscvqpdp(DisasContext *ctx)
+static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
{
- TCGv_i32 opc;
+ TCGv_i32 ro;
TCGv_ptr xt, xb;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- opc = tcg_const_i32(ctx->opcode);
- xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
- xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
- gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
- tcg_temp_free_i32(opc);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ ro = tcg_const_i32(a->rc);
+
+ xt = gen_avr_ptr(a->rt);
+ xb = gen_avr_ptr(a->rb);
+ gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
+ tcg_temp_free_i32(ro);
tcg_temp_free_ptr(xt);
tcg_temp_free_ptr(xb);
+
+ return true;
}
#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index f980bc1bae47..c974324c4c82 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 079/102] target/ppc: Fix e6500 boot
2021-12-15 17:02 ` Cédric Le Goater
` (64 preceding siblings ...)
2021-12-15 17:03 ` [PULL 078/102] target/ppc: move xscvqpdp to decodetree Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" Cédric Le Goater
` (22 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater, mario,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is the IVOR
for VPU. This is because QEMU knows only knows about the VPU interrupt
for the 7400s. In theory, we should not be raising _that_ VPU
interrupt, but instead another one specific for the e6500.
We unfortunately cannot register e6500-specific VPU/VPUA interrupts
because the SPEU/EFPDI interrupts also use IVOR32/33. These are
present only in the e500v1/2 versions. From the user manual:
e500v1, e500v2: only SPEU/EFPDI/EFPRI
e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA
e6500: only VPU/VPUA
So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code
to convert the VPU #73 to a #32 when we're in the e6500. Since the
handling for SPEU and VPU is the same this is the only change that's
needed. The EFPDI is not implemented and will cause an abort. I don't
think it worth it changing the error message to take VPUA into
consideration, so I'm not changing anything there.
This bug was discussed in the thread:
https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html
1- https://git.kernel.org/torvalds/c/cd66cc2ee52
Reported-by: <mario@locati.it>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 6 ++++++
target/ppc/excp_helper.c | 12 +++++++++++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 96034889dd02..c8e6868389cb 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2065,8 +2065,14 @@ static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
+ /*
+ * These two are the same IVOR as POWERPC_EXCP_VPU and
+ * POWERPC_EXCP_VPUA. We deal with that when dispatching at
+ * powerpc_excp().
+ */
env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
+
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
env->ivor_mask = 0x0000FFF7UL;
env->ivpr_mask = ivpr_mask;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index cbd88f74c9df..feb3fd42e26c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -344,6 +344,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
excp = POWERPC_EXCP_PROGRAM;
}
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
switch (excp) {
case POWERPC_EXCP_NONE:
/* Should never happen */
@@ -569,7 +579,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
}
break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"
2021-12-15 17:02 ` Cédric Le Goater
` (65 preceding siblings ...)
2021-12-15 17:03 ` [PULL 079/102] target/ppc: Fix e6500 boot Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 081/102] target/ppc: do not silence SNaN in xscvspdpn Cédric Le Goater
` (21 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater,
Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index feb3fd42e26c..6ba0840e9935 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -464,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
/*
- * Get rS/rD and rA from faulting opcode.
- * Note: We will only invoke ALIGN for atomic operations,
- * so all instructions are X-form.
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
*/
- {
- uint32_t insn = cpu_ldl_code(env, env->nip);
- env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
- }
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@@ -1441,6 +1439,11 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
+ uint32_t insn;
+
+ /* Restore state and reload the insn we executed, for filling in DSISR. */
+ cpu_restore_state(cs, retaddr, true);
+ insn = cpu_ldl_code(env, env->nip);
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
@@ -1456,8 +1459,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
}
cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = 0;
- cpu_loop_exit_restore(cs, retaddr);
+ env->error_code = insn & 0x03FF0000;
+ cpu_loop_exit(cs);
}
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 081/102] target/ppc: do not silence SNaN in xscvspdpn
2021-12-15 17:02 ` Cédric Le Goater
` (66 preceding siblings ...)
2021-12-15 17:03 ` [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers Cédric Le Goater
` (20 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Richard Henderson,
Matheus Ferst, Philippe Mathieu-Daudé
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmetic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[ clg: Fixed spelling in commit log ]
Message-Id: <20211214144459.1086343-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 5 +---
tests/tcg/ppc64le/non_signalling_xscv.c | 36 +++++++++++++++++++++++++
tests/tcg/ppc64/Makefile.target | 4 +--
tests/tcg/ppc64le/Makefile.target | 4 +--
4 files changed, 41 insertions(+), 8 deletions(-)
create mode 100644 tests/tcg/ppc64le/non_signalling_xscv.c
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 700c79156b06..e5c29b53b8b5 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2816,10 +2816,7 @@ uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
{
- float_status tstat = env->fp_status;
- set_float_exception_flags(0, &tstat);
-
- return float32_to_float64(xb >> 32, &tstat);
+ return helper_todouble(xb >> 32);
}
/*
diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c
new file mode 100644
index 000000000000..77f07033335d
--- /dev/null
+++ b/tests/tcg/ppc64le/non_signalling_xscv.c
@@ -0,0 +1,36 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <assert.h>
+
+#define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
+ do { \
+ __uint128_t t, b = B_HI; \
+ b <<= 64; \
+ b |= B_LO; \
+ asm(INSN " %x0, %x1\n\t" \
+ : "=wa" (t) \
+ : "wa" (b)); \
+ printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
+ "%016" PRIx64 "\n", (uint64_t)(b >> 64), (uint64_t)b, \
+ (uint64_t)(t >> 64), (uint64_t)t); \
+ assert((uint64_t)(t >> 64) == T_HI && (uint64_t)t == T_LO); \
+ } while (0)
+
+int main(void)
+{
+#ifndef __SIZEOF_INT128__
+ puts("__uint128_t not available, skipping...\n");
+#else
+ /* SNaN shouldn't be silenced */
+ TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0);
+ TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0);
+
+ /*
+ * SNaN inputs having no significant bits in the upper 23 bits of the
+ * signifcand will return Infinity as the result.
+ */
+ TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0);
+#endif
+ return 0;
+}
diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
index 8f4c7ac4ed7d..0368007028c9 100644
--- a/tests/tcg/ppc64/Makefile.target
+++ b/tests/tcg/ppc64/Makefile.target
@@ -6,9 +6,9 @@ VPATH += $(SRC_PATH)/tests/tcg/ppc64
VPATH += $(SRC_PATH)/tests/tcg/ppc64le
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER8_VECTOR),)
-PPC64_TESTS=bcdsub
+PPC64_TESTS=bcdsub non_signalling_xscv
endif
-bcdsub: CFLAGS += -mpower8-vector
+$(PPC64_TESTS): CFLAGS += -mpower8-vector
PPC64_TESTS += byte_reverse
PPC64_TESTS += mtfsf
diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target
index e031f65adcb3..480ff0898d7e 100644
--- a/tests/tcg/ppc64le/Makefile.target
+++ b/tests/tcg/ppc64le/Makefile.target
@@ -5,9 +5,9 @@
VPATH += $(SRC_PATH)/tests/tcg/ppc64le
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER8_VECTOR),)
-PPC64LE_TESTS=bcdsub
+PPC64LE_TESTS=bcdsub non_signalling_xscv
endif
-bcdsub: CFLAGS += -mpower8-vector
+$(PPC64LE_TESTS): CFLAGS += -mpower8-vector
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
PPC64LE_TESTS += byte_reverse
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers
2021-12-15 17:02 ` Cédric Le Goater
` (67 preceding siblings ...)
2021-12-15 17:03 ` [PULL 081/102] target/ppc: do not silence SNaN in xscvspdpn Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 083/102] target/ppc: PMU basic cycle count for pseries TCG Cédric Le Goater
` (19 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are
inactive due to frozen counter bits state are of type
'PMU_EVENT_INACTIVE'. Other types added in this patch are
PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added
later on.
Let's also add the required PMU cycle overflow timers. They will be used
to trigger cycle overflows when cycle events are being sampled. This
timer will call cpu_ppc_pmu_timer_cb(), which in turn calls
fire_PMC_interrupt(). Both functions are stubs that will be implemented
later on when EBB support is added.
Two new helper files are created to host this new logic.
cpu_ppc_pmu_init() will init all overflow timers during CPU init time.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 15 ++++++++++
target/ppc/power8-pmu.h | 25 +++++++++++++++++
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/cpu_init.c | 24 ++++++++++++++++
target/ppc/power8-pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++
target/ppc/meson.build | 1 +
6 files changed, 128 insertions(+)
create mode 100644 target/ppc/power8-pmu.h
create mode 100644 target/ppc/power8-pmu.c
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c07a8e9f7d4b..39fadca564bb 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -296,6 +296,15 @@ typedef struct ppc_v3_pate_t {
uint64_t dw1;
} ppc_v3_pate_t;
+/* PMU related structs and defines */
+#define PMU_COUNTERS_NUM 6
+typedef enum {
+ PMU_EVENT_INVALID = 0,
+ PMU_EVENT_INACTIVE,
+ PMU_EVENT_CYCLES,
+ PMU_EVENT_INSTRUCTIONS,
+} PMUEventType;
+
/*****************************************************************************/
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
@@ -1195,6 +1204,12 @@ struct CPUPPCState {
uint32_t tm_vscr;
uint64_t tm_dscr;
uint64_t tm_tar;
+
+ /*
+ * Timers used to fire performance monitor alerts
+ * when counting cycles.
+ */
+ QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
new file mode 100644
index 000000000000..49a813a443d7
--- /dev/null
+++ b/target/ppc/power8-pmu.h
@@ -0,0 +1,25 @@
+/*
+ * PMU emulation helpers for TCG IBM POWER chips
+ *
+ * Copyright IBM Corp. 2021
+ *
+ * Authors:
+ * Daniel Henrique Barboza <danielhb413@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef POWER8_PMU
+#define POWER8_PMU
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+
+void cpu_ppc_pmu_init(CPUPPCState *env);
+
+#endif
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 58e7341cb784..a57ba70a8781 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -20,6 +20,7 @@
#include "target/ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target/ppc/mmu-hash64.h"
+#include "target/ppc/power8-pmu.h"
#include "sysemu/numa.h"
#include "sysemu/reset.h"
#include "sysemu/hw_accel.h"
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c8e6868389cb..7c47ffd6e19b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -45,6 +45,7 @@
#include "helper_regs.h"
#include "internal.h"
#include "spr_tcg.h"
+#include "power8-pmu.h"
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
@@ -6810,6 +6811,20 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
#endif
}
+/*
+ * Initialize PMU counter overflow timers for Power8 and
+ * newer Power chips when using TCG.
+ */
+static void init_tcg_pmu_power8(CPUPPCState *env)
+{
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+ /* Init PMU overflow timers */
+ if (!kvm_enabled()) {
+ cpu_ppc_pmu_init(env);
+ }
+#endif
+}
+
static void init_proc_book3s_common(CPUPPCState *env)
{
register_ne_601_sprs(env);
@@ -7127,6 +7142,9 @@ static void init_proc_POWER8(CPUPPCState *env)
register_sdr1_sprs(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_rmor_sprs(env);
@@ -7321,6 +7339,9 @@ static void init_proc_POWER9(CPUPPCState *env)
init_proc_book3s_common(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_amr_sprs(env);
@@ -7537,6 +7558,9 @@ static void init_proc_POWER10(CPUPPCState *env)
init_proc_book3s_common(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_amr_sprs(env);
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
new file mode 100644
index 000000000000..d443bcb6c6ca
--- /dev/null
+++ b/target/ppc/power8-pmu.c
@@ -0,0 +1,62 @@
+/*
+ * PMU emulation helpers for TCG IBM POWER chips
+ *
+ * Copyright IBM Corp. 2021
+ *
+ * Authors:
+ * Daniel Henrique Barboza <danielhb413@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "power8-pmu.h"
+#include "cpu.h"
+#include "helper_regs.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "hw/ppc/ppc.h"
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+static void fire_PMC_interrupt(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) {
+ return;
+ }
+
+ /* PMC interrupt not implemented yet */
+ return;
+}
+
+static void cpu_ppc_pmu_timer_cb(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ fire_PMC_interrupt(cpu);
+}
+
+void cpu_ppc_pmu_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ int i, sprn;
+
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
+ if (sprn == SPR_POWER_PMC5) {
+ continue;
+ }
+
+ i = sprn - SPR_POWER_PMC1;
+
+ env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ &cpu_ppc_pmu_timer_cb,
+ cpu);
+ }
+}
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index b85f29570391..a49a8911e069 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -51,6 +51,7 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files(
'mmu-book3s-v3.c',
'mmu-hash64.c',
'mmu-radix64.c',
+ 'power8-pmu.c',
))
target_arch += {'ppc': ppc_ss}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 083/102] target/ppc: PMU basic cycle count for pseries TCG
2021-12-15 17:02 ` Cédric Le Goater
` (68 preceding siblings ...)
2021-12-15 17:03 ` [PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w Cédric Le Goater
` (18 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 20 ++++++
target/ppc/helper.h | 1 +
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 6 +-
target/ppc/power8-pmu.c | 110 +++++++++++++++++++++++++++++++
target/ppc/power8-pmu-regs.c.inc | 23 ++++++-
6 files changed, 157 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 39fadca564bb..69cfb2e5f930 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -360,6 +360,9 @@ typedef enum {
#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
#define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
#define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
+#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
+#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
+#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */
@@ -372,6 +375,17 @@ typedef enum {
#define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
+#define MMCR1_EVT_SIZE 8
+/* extract64() does a right shift before extracting */
+#define MMCR1_PMC1SEL_START 32
+#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
+#define MMCR1_PMC2SEL_START 40
+#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
+#define MMCR1_PMC3SEL_START 48
+#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
+#define MMCR1_PMC4SEL_START 56
+#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
@@ -1210,6 +1224,12 @@ struct CPUPPCState {
* when counting cycles.
*/
QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
+
+ /*
+ * PMU base time value used by the PMU to calculate
+ * running cycles.
+ */
+ uint64_t pmu_base_time;
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d166323b641c..0e6cf2d09d4e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -20,6 +20,7 @@ DEF_HELPER_1(rfscv, void, env)
DEF_HELPER_1(hrfid, void, env)
DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
+DEF_HELPER_2(store_mmcr0, void, env, tl)
#endif
DEF_HELPER_1(check_tlb_flush_local, void, env)
DEF_HELPER_1(check_tlb_flush_global, void, env)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 520f1ef23336..eb1d0c2bf0dc 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -25,6 +25,7 @@
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
+void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7c47ffd6e19b..cfa605a76b84 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6254,8 +6254,8 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
{
spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCR0, 0x00000000);
+ &spr_read_generic, &spr_write_MMCR0,
+ KVM_REG_PPC_MMCR0, 0x80000000);
spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -6303,7 +6303,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState *env)
spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
&spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
&spr_read_ureg, &spr_write_ureg,
- 0x00000000);
+ 0x80000000);
spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, &spr_write_ureg,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index d443bcb6c6ca..5e689144d712 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -23,6 +23,116 @@
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static bool pmc_is_inactive(CPUPPCState *env, int sprn)
+{
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
+ return true;
+ }
+
+ if (sprn < SPR_POWER_PMC5) {
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14;
+ }
+
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56;
+}
+
+/*
+ * For PMCs 1-4, IBM POWER chips has support for an implementation
+ * dependent event, 0x1E, that enables cycle counting. The Linux kernel
+ * makes extensive use of 0x1E, so let's also support it.
+ *
+ * Likewise, event 0x2 is an implementation-dependent event that IBM
+ * POWER chips implement (at least since POWER8) that is equivalent to
+ * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well.
+ */
+static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
+{
+ uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR,
+ MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR };
+ PMUEventType evt_type = PMU_EVENT_INVALID;
+ uint8_t pmcsel;
+ int i;
+
+ if (pmc_is_inactive(env, sprn)) {
+ return PMU_EVENT_INACTIVE;
+ }
+
+ if (sprn == SPR_POWER_PMC5) {
+ return PMU_EVENT_INSTRUCTIONS;
+ }
+
+ if (sprn == SPR_POWER_PMC6) {
+ return PMU_EVENT_CYCLES;
+ }
+
+ i = sprn - SPR_POWER_PMC1;
+ pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i],
+ MMCR1_EVT_SIZE);
+
+ switch (pmcsel) {
+ case 0x2:
+ evt_type = PMU_EVENT_INSTRUCTIONS;
+ break;
+ case 0x1E:
+ evt_type = PMU_EVENT_CYCLES;
+ break;
+ case 0xF0:
+ /*
+ * PMC1SEL = 0xF0 is the architected PowerISA v3.1
+ * event that counts cycles using PMC1.
+ */
+ if (sprn == SPR_POWER_PMC1) {
+ evt_type = PMU_EVENT_CYCLES;
+ }
+ break;
+ case 0xFE:
+ /*
+ * PMC1SEL = 0xFE is the architected PowerISA v3.1
+ * event to sample instructions using PMC1.
+ */
+ if (sprn == SPR_POWER_PMC1) {
+ evt_type = PMU_EVENT_INSTRUCTIONS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return evt_type;
+}
+
+static void pmu_update_cycles(CPUPPCState *env)
+{
+ uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ uint64_t time_delta = now - env->pmu_base_time;
+ int sprn;
+
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
+ if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) {
+ continue;
+ }
+
+ /*
+ * The pseries and powernv clock runs at 1Ghz, meaning
+ * that 1 nanosec equals 1 cycle.
+ */
+ env->spr[sprn] += time_delta;
+ }
+
+ /* Update base_time for future calculations */
+ env->pmu_base_time = now;
+}
+
+void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
+{
+ pmu_update_cycles(env);
+
+ env->spr[SPR_POWER_MMCR0] = value;
+
+ /* MMCR0 writes can change HFLAGS_PMCCCLEAR */
+ hreg_compute_hflags(env);
+}
+
static void fire_PMC_interrupt(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 739185123827..fbb89776414e 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -104,6 +104,17 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
tcg_temp_free(t0);
}
+static void write_MMCR0_common(DisasContext *ctx, TCGv val)
+{
+ /*
+ * helper_store_mmcr0 will make clock based operations that
+ * will cause 'bad icount read' errors if we do not execute
+ * gen_icount_io_start() beforehand.
+ */
+ gen_icount_io_start(ctx);
+ gen_helper_store_mmcr0(cpu_env, val);
+}
+
void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
{
TCGv masked_gprn;
@@ -119,7 +130,7 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
*/
masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0,
MMCR0_UREG_MASK);
- gen_store_spr(SPR_POWER_MMCR0, masked_gprn);
+ write_MMCR0_common(ctx, masked_gprn);
tcg_temp_free(masked_gprn);
}
@@ -219,6 +230,11 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
/* The remaining steps are similar to PMCs 1-4 userspace write */
spr_write_PMC14_ureg(ctx, sprn, gprn);
}
+
+void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
+{
+ write_MMCR0_common(ctx, cpu_gpr[gprn]);
+}
#else
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
{
@@ -259,4 +275,9 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
{
spr_noaccess(ctx, gprn, sprn);
}
+
+void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+}
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w
2021-12-15 17:02 ` Cédric Le Goater
` (69 preceding siblings ...)
2021-12-15 17:03 ` [PULL 083/102] target/ppc: PMU basic cycle count for pseries TCG Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write Cédric Le Goater
` (17 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the required wiring for that and make our lives a bit easier in the
next patches.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 2 ++
target/ppc/spr_tcg.h | 2 ++
target/ppc/cpu_init.c | 12 ++++++------
target/ppc/power8-pmu.c | 14 ++++++++++++++
target/ppc/power8-pmu-regs.c.inc | 29 +++++++++++++++++++++++++++--
5 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0e6cf2d09d4e..984d03181a52 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -21,6 +21,8 @@ DEF_HELPER_1(hrfid, void, env)
DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
+DEF_HELPER_3(store_pmc, void, env, i32, i64)
+DEF_HELPER_2(read_pmc, tl, env, i32)
#endif
DEF_HELPER_1(check_tlb_flush_local, void, env)
DEF_HELPER_1(check_tlb_flush_global, void, env)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index eb1d0c2bf0dc..1e79a0522aac 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
@@ -35,6 +36,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gprn);
void spr_read_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn);
+void spr_read_PMC(DisasContext *ctx, int gprn, int sprn);
void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn);
void spr_read_tbl(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cfa605a76b84..ceb325b311fb 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6266,27 +6266,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
KVM_REG_PPC_MMCRA, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC1, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC2, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC3, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC4, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC5, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_PMC, &spr_write_PMC,
KVM_REG_PPC_PMC6, 0x00000000);
spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 5e689144d712..7131f52ccc5d 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -133,6 +133,20 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
hreg_compute_hflags(env);
}
+target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
+{
+ pmu_update_cycles(env);
+
+ return env->spr[sprn];
+}
+
+void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
+{
+ pmu_update_cycles(env);
+
+ env->spr[sprn] = value;
+}
+
static void fire_PMC_interrupt(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index fbb89776414e..f0c9cc343b3d 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -181,13 +181,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(masked_gprn);
}
+void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
+{
+ TCGv_i32 t_sprn = tcg_const_i32(sprn);
+
+ gen_icount_io_start(ctx);
+ gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
+
+ tcg_temp_free_i32(t_sprn);
+}
+
void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
{
if (!spr_groupA_read_allowed(ctx)) {
return;
}
- spr_read_ureg(ctx, gprn, sprn);
+ spr_read_PMC(ctx, gprn, sprn + 0x10);
}
void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
@@ -206,13 +216,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
spr_read_PMC14_ureg(ctx, gprn, sprn);
}
+void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv_i32 t_sprn = tcg_const_i32(sprn);
+
+ gen_icount_io_start(ctx);
+ gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
+
+ tcg_temp_free_i32(t_sprn);
+}
+
void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
{
if (!spr_groupA_write_allowed(ctx)) {
return;
}
- spr_write_ureg(ctx, sprn, gprn);
+ spr_write_PMC(ctx, sprn + 0x10, gprn);
}
void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
@@ -280,4 +300,9 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic(ctx, sprn, gprn);
}
+
+void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+}
#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write
2021-12-15 17:02 ` Cédric Le Goater
` (70 preceding siblings ...)
2021-12-15 17:03 ` [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events Cédric Le Goater
` (16 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to
control the PMU. These three registers aren't being handled in this
initial implementation, so for now we're controlling all the PMU
aspects using MMCR0, MMCR1 and the PMCs.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/power8-pmu.c | 7 +++++++
target/ppc/power8-pmu-regs.c.inc | 11 +++++++++++
5 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 984d03181a52..77c85e1292fa 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env)
DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
+DEF_HELPER_2(store_mmcr1, void, env, tl)
DEF_HELPER_3(store_pmc, void, env, i32, i64)
DEF_HELPER_2(read_pmc, tl, env, i32)
#endif
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 1e79a0522aac..1d6521eedc83 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ceb325b311fb..e865d368f237 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6258,7 +6258,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
KVM_REG_PPC_MMCR0, 0x80000000);
spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_MMCR1,
KVM_REG_PPC_MMCR1, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 7131f52ccc5d..73252529beee 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -133,6 +133,13 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
hreg_compute_hflags(env);
}
+void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
+{
+ pmu_update_cycles(env);
+
+ env->spr[SPR_POWER_MMCR1] = value;
+}
+
target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
{
pmu_update_cycles(env);
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index f0c9cc343b3d..25b13ad56434 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -255,6 +255,12 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
{
write_MMCR0_common(ctx, cpu_gpr[gprn]);
}
+
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_icount_io_start(ctx);
+ gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
+}
#else
void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
{
@@ -301,6 +307,11 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
spr_write_generic(ctx, sprn, gprn);
}
+void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+}
+
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic(ctx, sprn, gprn);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events
2021-12-15 17:02 ` Cédric Le Goater
` (71 preceding siblings ...)
2021-12-15 17:03 ` [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 087/102] target/ppc: enable PMU instruction count Cédric Le Goater
` (15 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.
For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer to expire in the moment the overflow would be occuring. The
timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will
trigger the PMU alert and, if the conditions are met, an EBB exception.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 2 ++
target/ppc/power8-pmu.c | 71 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 69cfb2e5f930..cf637f0f6dfb 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,8 @@ typedef enum {
#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
+#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
+#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 73252529beee..399234a2fce8 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -23,6 +23,8 @@
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
+
static bool pmc_is_inactive(CPUPPCState *env, int sprn)
{
if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
@@ -36,6 +38,15 @@ static bool pmc_is_inactive(CPUPPCState *env, int sprn)
return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56;
}
+static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn)
+{
+ if (sprn == SPR_POWER_PMC1) {
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE;
+ }
+
+ return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
+}
+
/*
* For PMCs 1-4, IBM POWER chips has support for an implementation
* dependent event, 0x1E, that enables cycle counting. The Linux kernel
@@ -123,6 +134,61 @@ static void pmu_update_cycles(CPUPPCState *env)
env->pmu_base_time = now;
}
+/*
+ * Helper function to retrieve the cycle overflow timer of the
+ * 'sprn' counter.
+ */
+static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn)
+{
+ return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1];
+}
+
+static void pmc_update_overflow_timer(CPUPPCState *env, int sprn)
+{
+ QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn);
+ int64_t timeout;
+
+ /*
+ * PMC5 does not have an overflow timer and this pointer
+ * will be NULL.
+ */
+ if (!pmc_overflow_timer) {
+ return;
+ }
+
+ if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES ||
+ !pmc_has_overflow_enabled(env, sprn)) {
+ /* Overflow timer is not needed for this counter */
+ timer_del(pmc_overflow_timer);
+ return;
+ }
+
+ if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) {
+ timeout = 0;
+ } else {
+ timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn];
+ }
+
+ /*
+ * Use timer_mod_anticipate() because an overflow timer might
+ * be already running for this PMC.
+ */
+ timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout);
+}
+
+static void pmu_update_overflow_timers(CPUPPCState *env)
+{
+ int sprn;
+
+ /*
+ * Scroll through all PMCs and start counter overflow timers for
+ * PM_CYC events, if needed.
+ */
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
+ pmc_update_overflow_timer(env, sprn);
+ }
+}
+
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
{
pmu_update_cycles(env);
@@ -131,6 +197,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
/* MMCR0 writes can change HFLAGS_PMCCCLEAR */
hreg_compute_hflags(env);
+
+ /* Update cycle overflow timers with the current MMCR0 state */
+ pmu_update_overflow_timers(env);
}
void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
@@ -152,6 +221,8 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
pmu_update_cycles(env);
env->spr[sprn] = value;
+
+ pmc_update_overflow_timer(env, sprn);
}
static void fire_PMC_interrupt(PowerPCCPU *cpu)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 087/102] target/ppc: enable PMU instruction count
2021-12-15 17:02 ` Cédric Le Goater
` (72 preceding siblings ...)
2021-12-15 17:03 ` [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event Cédric Le Goater
` (14 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated in
each translation block right before exiting it.
A new pmu_count_insns() helper in translation.c was added to do that.
After verifying that the PMU is counting instructions, call
helper_insns_inc(). This new helper from power8-pmu.c will add the
instructions to the relevant counters. It'll also be responsible for
triggering counter negative overflows as it is already being done with
cycles.
To verify whether the PMU is counting instructions or now, a new hflags
named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal
state of the PMU. We're be using this flag to avoid calling
helper_insn_inc() when we do not have a valid instruction event being
sampled.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 1 +
target/ppc/helper.h | 1 +
target/ppc/power8-pmu.h | 1 +
target/ppc/helper_regs.c | 7 ++++
target/ppc/power8-pmu.c | 67 +++++++++++++++++++++++++++++++-
target/ppc/translate.c | 64 ++++++++++++++++++++++++++++++
target/ppc/power8-pmu-regs.c.inc | 6 +++
7 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cf637f0f6dfb..313b16f39273 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -655,6 +655,7 @@ enum {
HFLAGS_PR = 14, /* MSR_PR */
HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
+ HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */
HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 77c85e1292fa..13d8305a08bf 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -24,6 +24,7 @@ DEF_HELPER_2(store_mmcr0, void, env, tl)
DEF_HELPER_2(store_mmcr1, void, env, tl)
DEF_HELPER_3(store_pmc, void, env, i32, i64)
DEF_HELPER_2(read_pmc, tl, env, i32)
+DEF_HELPER_2(insns_inc, void, env, i32)
#endif
DEF_HELPER_1(check_tlb_flush_local, void, env)
DEF_HELPER_1(check_tlb_flush_global, void, env)
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
index 49a813a443d7..3ee4b4cda5a9 100644
--- a/target/ppc/power8-pmu.h
+++ b/target/ppc/power8-pmu.h
@@ -21,5 +21,6 @@
#include "qemu/main-loop.h"
void cpu_ppc_pmu_init(CPUPPCState *env);
+bool pmu_insn_cnt_enabled(CPUPPCState *env);
#endif
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 99562edd5741..b8479288426b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
+#include "power8-pmu.h"
/* Swap temporary saved registers with GPRs */
void hreg_swap_gpr_tgpr(CPUPPCState *env)
@@ -121,6 +122,12 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
hflags |= 1 << HFLAGS_HV;
}
+#if defined(TARGET_PPC64)
+ if (pmu_insn_cnt_enabled(env)) {
+ hflags |= 1 << HFLAGS_INSN_CNT;
+ }
+#endif
+
/*
* This is our encoding for server processors. The architecture
* specifies that there is no such thing as userspace with
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 399234a2fce8..e163ba564012 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -112,6 +112,54 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
return evt_type;
}
+bool pmu_insn_cnt_enabled(CPUPPCState *env)
+{
+ int sprn;
+
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
+ if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
+{
+ bool overflow_triggered = false;
+ int sprn;
+
+ /* PMC6 never counts instructions */
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
+ if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) {
+ continue;
+ }
+
+ env->spr[sprn] += num_insns;
+
+ if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
+ pmc_has_overflow_enabled(env, sprn)) {
+
+ overflow_triggered = true;
+
+ /*
+ * The real PMU will always trigger a counter overflow with
+ * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to
+ * do that since we're counting block of instructions at
+ * the end of each translation block, and we're probably
+ * passing this value at this point.
+ *
+ * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed
+ * counter to simulate what the real hardware would do.
+ */
+ env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL;
+ }
+ }
+
+ return overflow_triggered;
+}
+
static void pmu_update_cycles(CPUPPCState *env)
{
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -195,7 +243,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
env->spr[SPR_POWER_MMCR0] = value;
- /* MMCR0 writes can change HFLAGS_PMCCCLEAR */
+ /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */
hreg_compute_hflags(env);
/* Update cycle overflow timers with the current MMCR0 state */
@@ -207,6 +255,9 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
pmu_update_cycles(env);
env->spr[SPR_POWER_MMCR1] = value;
+
+ /* MMCR1 writes can change HFLAGS_INSN_CNT */
+ hreg_compute_hflags(env);
}
target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
@@ -237,6 +288,20 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
return;
}
+/* This helper assumes that the PMC is running. */
+void helper_insns_inc(CPUPPCState *env, uint32_t num_insns)
+{
+ bool overflow_triggered;
+ PowerPCCPU *cpu;
+
+ overflow_triggered = pmu_increment_insns(env, num_insns);
+
+ if (overflow_triggered) {
+ cpu = env_archcpu(env);
+ fire_PMC_interrupt(cpu);
+ }
+}
+
static void cpu_ppc_pmu_timer_cb(void *opaque)
{
PowerPCCPU *cpu = opaque;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b3f3b408db18..633b907058e4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -177,6 +177,7 @@ struct DisasContext {
bool hr;
bool mmcr0_pmcc0;
bool mmcr0_pmcc1;
+ bool pmu_insn_cnt;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint32_t flags;
@@ -4170,6 +4171,49 @@ static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
#endif
}
+#if defined(TARGET_PPC64)
+static void pmu_count_insns(DisasContext *ctx)
+{
+ /*
+ * Do not bother calling the helper if the PMU isn't counting
+ * instructions.
+ */
+ if (!ctx->pmu_insn_cnt) {
+ return;
+ }
+
+ #if !defined(CONFIG_USER_ONLY)
+ /*
+ * The PMU insns_inc() helper stops the internal PMU timer if a
+ * counter overflows happens. In that case, if the guest is
+ * running with icount and we do not handle it beforehand,
+ * the helper can trigger a 'bad icount read'.
+ */
+ gen_icount_io_start(ctx);
+
+ gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
+#else
+ /*
+ * User mode can read (but not write) PMC5 and start/stop
+ * the PMU via MMCR0_FC. In this case just increment
+ * PMC5 with base.num_insns.
+ */
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_spr(t0, SPR_POWER_PMC5);
+ tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
+ gen_store_spr(SPR_POWER_PMC5, t0);
+
+ tcg_temp_free(t0);
+#endif /* #if !defined(CONFIG_USER_ONLY) */
+}
+#else
+static void pmu_count_insns(DisasContext *ctx)
+{
+ return;
+}
+#endif /* #if defined(TARGET_PPC64) */
+
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
return translator_use_goto_tb(&ctx->base, dest);
@@ -4180,6 +4224,14 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
if (unlikely(ctx->singlestep_enabled)) {
gen_debug_exception(ctx);
} else {
+ /*
+ * tcg_gen_lookup_and_goto_ptr will exit the TB if
+ * CF_NO_GOTO_PTR is set. Count insns now.
+ */
+ if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
+ pmu_count_insns(ctx);
+ }
+
tcg_gen_lookup_and_goto_ptr();
}
}
@@ -4191,6 +4243,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
dest = (uint32_t) dest;
}
if (use_goto_tb(ctx, dest)) {
+ pmu_count_insns(ctx);
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_nip, dest & ~3);
tcg_gen_exit_tb(ctx->base.tb, n);
@@ -8432,6 +8485,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->hr = (hflags >> HFLAGS_HR) & 1;
ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
+ ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
ctx->singlestep_enabled = 0;
if ((hflags >> HFLAGS_SE) & 1) {
@@ -8538,6 +8592,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
switch (is_jmp) {
case DISAS_TOO_MANY:
if (use_goto_tb(ctx, nip)) {
+ pmu_count_insns(ctx);
tcg_gen_goto_tb(0);
gen_update_nip(ctx, nip);
tcg_gen_exit_tb(ctx->base.tb, 0);
@@ -8548,6 +8603,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
gen_update_nip(ctx, nip);
/* fall through */
case DISAS_CHAIN:
+ /*
+ * tcg_gen_lookup_and_goto_ptr will exit the TB if
+ * CF_NO_GOTO_PTR is set. Count insns now.
+ */
+ if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
+ pmu_count_insns(ctx);
+ }
+
tcg_gen_lookup_and_goto_ptr();
break;
@@ -8555,6 +8618,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
gen_update_nip(ctx, nip);
/* fall through */
case DISAS_EXIT:
+ pmu_count_insns(ctx);
tcg_gen_exit_tb(NULL, 0);
break;
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 25b13ad56434..2bab6cece709 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -113,6 +113,12 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val)
*/
gen_icount_io_start(ctx);
gen_helper_store_mmcr0(cpu_env, val);
+
+ /*
+ * End the translation block because MMCR0 writes can change
+ * ctx->pmu_insn_cnt.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
2021-12-15 17:02 ` Cédric Le Goater
` (73 preceding siblings ...)
2021-12-15 17:03 ` [PULL 087/102] target/ppc: enable PMU instruction count Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 089/102] PPC64/TCG: Implement 'rfebb' instruction Cédric Le Goater
` (13 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 4 ++++
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/power8-pmu.c | 27 ++++++++++++++++++++++++---
target/ppc/translate.c | 12 ++++++++++++
5 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 313b16f39273..b0473526ced0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -303,6 +303,7 @@ typedef enum {
PMU_EVENT_INACTIVE,
PMU_EVENT_CYCLES,
PMU_EVENT_INSTRUCTIONS,
+ PMU_EVENT_INSN_RUN_LATCH,
} PMUEventType;
/*****************************************************************************/
@@ -388,6 +389,9 @@ typedef enum {
#define MMCR1_PMC4SEL_START 56
#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
+/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
+#define CTRL_RUN PPC_BIT(63)
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 1d6521eedc83..f98d97c0ba17 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e865d368f237..06ef15cd9e4e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6182,7 +6182,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
+ SPR_NOACCESS, &spr_write_CTRL,
0x00000000);
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
&spr_read_ureg, SPR_NOACCESS,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index e163ba564012..08d1902cd5d6 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
evt_type = PMU_EVENT_CYCLES;
}
break;
+ case 0xFA:
+ /*
+ * PMC4SEL = 0xFA is the "instructions completed
+ * with run latch set" event.
+ */
+ if (sprn == SPR_POWER_PMC4) {
+ evt_type = PMU_EVENT_INSN_RUN_LATCH;
+ }
+ break;
case 0xFE:
/*
* PMC1SEL = 0xFE is the architected PowerISA v3.1
@@ -117,7 +126,8 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env)
int sprn;
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
- if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) {
+ if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS ||
+ pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) {
return true;
}
}
@@ -132,11 +142,22 @@ static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
/* PMC6 never counts instructions */
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
- if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) {
+ PMUEventType evt_type = pmc_get_event(env, sprn);
+ bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS ||
+ evt_type == PMU_EVENT_INSN_RUN_LATCH;
+
+ if (pmc_is_inactive(env, sprn) || !insn_event) {
continue;
}
- env->spr[sprn] += num_insns;
+ if (evt_type == PMU_EVENT_INSTRUCTIONS) {
+ env->spr[sprn] += num_insns;
+ }
+
+ if (evt_type == PMU_EVENT_INSN_RUN_LATCH &&
+ env->spr[SPR_CTRL] & CTRL_RUN) {
+ env->spr[sprn] += num_insns;
+ }
if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
pmc_has_overflow_enabled(env, sprn)) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 633b907058e4..68fbbf67ecb4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -403,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
spr_store_dump_spr(sprn);
}
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+
+ /*
+ * SPR_CTRL writes must force a new translation block,
+ * allowing the PMU to calculate the run latch events with
+ * more accuracy.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+}
+
#if !defined(CONFIG_USER_ONLY)
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 089/102] PPC64/TCG: Implement 'rfebb' instruction
2021-12-15 17:02 ` Cédric Le Goater
` (74 preceding siblings ...)
2021-12-15 17:03 ` [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3 Cédric Le Goater
` (12 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater, Matheus Ferst, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The following operations happens during an EBB:
- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).
The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].
This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.
[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 13 ++++++++++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 5 ++++
target/ppc/excp_helper.c | 31 ++++++++++++++++++++++++
target/ppc/translate.c | 2 ++
target/ppc/translate/branch-impl.c.inc | 33 ++++++++++++++++++++++++++
6 files changed, 85 insertions(+)
create mode 100644 target/ppc/translate/branch-impl.c.inc
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b0473526ced0..fc66c3561dab 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -392,6 +392,19 @@ typedef enum {
/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
#define CTRL_RUN PPC_BIT(63)
+/* EBB/BESCR bits */
+/* Global Enable */
+#define BESCR_GE PPC_BIT(0)
+/* External Event-based Exception Enable */
+#define BESCR_EE PPC_BIT(30)
+/* Performance Monitor Event-based Exception Enable */
+#define BESCR_PME PPC_BIT(31)
+/* External Event-based Exception Occurred */
+#define BESCR_EEO PPC_BIT(62)
+/* Performance Monitor Event-based Exception Occurred */
+#define BESCR_PMEO PPC_BIT(63)
+#define BESCR_INVALID PPC_BITMASK(32, 33)
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 13d8305a08bf..fb6cac38b4c5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32)
DEF_HELPER_1(rfid, void, env)
DEF_HELPER_1(rfscv, void, env)
DEF_HELPER_1(hrfid, void, env)
+DEF_HELPER_2(rfebb, void, env, tl)
DEF_HELPER_2(store_lpcr, void, env, tl)
DEF_HELPER_2(store_pcr, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8bdc059a4c79..2a9c91a4235e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -470,3 +470,8 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+
+### rfebb
+&XL_s s:uint8_t
+@XL_s ......-------------- s:1 .......... - &XL_s
+RFEBB 010011-------------- . 0010010010 - @XL_s
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6ba0840e9935..f90e616aacda 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1228,6 +1228,37 @@ void helper_hrfid(CPUPPCState *env)
}
#endif
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+void helper_rfebb(CPUPPCState *env, target_ulong s)
+{
+ target_ulong msr = env->msr;
+
+ /*
+ * Handling of BESCR bits 32:33 according to PowerISA v3.1:
+ *
+ * "If BESCR 32:33 != 0b00 the instruction is treated as if
+ * the instruction form were invalid."
+ */
+ if (env->spr[SPR_BESCR] & BESCR_INVALID) {
+ raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+ }
+
+ env->nip = env->spr[SPR_EBBRR];
+
+ /* Switching to 32-bit ? Crop the nip */
+ if (!msr_is_64bit(env, msr)) {
+ env->nip = (uint32_t)env->spr[SPR_EBBRR];
+ }
+
+ if (s) {
+ env->spr[SPR_BESCR] |= BESCR_GE;
+ } else {
+ env->spr[SPR_BESCR] &= ~BESCR_GE;
+ }
+}
+#endif
+
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
void helper_40x_rfci(CPUPPCState *env)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 68fbbf67ecb4..114456148c4b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7461,6 +7461,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/spe-impl.c.inc"
+#include "translate/branch-impl.c.inc"
+
/* Handles lfdp, lxsd, lxssp */
static void gen_dform39(DisasContext *ctx)
{
diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc
new file mode 100644
index 000000000000..29cfa11854fa
--- /dev/null
+++ b/target/ppc/translate/branch-impl.c.inc
@@ -0,0 +1,33 @@
+/*
+ * Power ISA decode for branch instructions
+ *
+ * Copyright IBM Corp. 2021
+ *
+ * Authors:
+ * Daniel Henrique Barboza <danielhb413@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
+
+ gen_icount_io_start(ctx);
+ gen_update_cfar(ctx, ctx->cia);
+ gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
+
+ ctx->base.is_jmp = DISAS_CHAIN;
+
+ return true;
+}
+#else
+static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
+{
+ gen_invalid(ctx);
+ return true;
+}
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3
2021-12-15 17:02 ` Cédric Le Goater
` (75 preceding siblings ...)
2021-12-15 17:03 ` [PULL 089/102] PPC64/TCG: Implement 'rfebb' instruction Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices Cédric Le Goater
` (11 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb3.h | 3 +++
hw/pci-host/pnv_phb3.c | 1 +
hw/ppc/pnv.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index e2a2e3624532..e9c13e6bd821 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -16,6 +16,7 @@
#include "qom/object.h"
typedef struct PnvPHB3 PnvPHB3;
+typedef struct PnvChip PnvChip;
/*
* PHB3 XICS Source for MSIs
@@ -157,6 +158,8 @@ struct PnvPHB3 {
PnvPHB3RootPort root;
QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
+
+ PnvChip *chip;
};
uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index a7f96850055a..3aa42ef9d4b9 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge,
static Property pnv_phb3_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
+ DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 44ae41a9cb6b..3e43c53376c7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1231,6 +1231,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
&error_fatal);
+ object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
+ &error_fatal);
if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
return;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices
2021-12-15 17:02 ` Cédric Le Goater
` (76 preceding siblings ...)
2021-12-15 17:03 ` [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3 Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 092/102] ppc/pnv: Drop the "num-phbs" property Cédric Le Goater
` (10 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 3aa42ef9d4b9..9c4451ca0d1c 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -993,7 +993,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
- if (phb->phb_id >= PNV8_CHIP_PHB3_MAX) {
+ if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) {
error_setg(errp, "invalid PHB index: %d", phb->phb_id);
return;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 092/102] ppc/pnv: Drop the "num-phbs" property
2021-12-15 17:02 ` Cédric Le Goater
` (77 preceding siblings ...)
2021-12-15 17:03 ` [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 093/102] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() Cédric Le Goater
` (9 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
It is never used.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3e43c53376c7..bbebd21d7522 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1771,7 +1771,6 @@ static Property pnv_chip_properties[] = {
DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
- DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 093/102] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
2021-12-15 17:02 ` Cédric Le Goater
` (78 preceding siblings ...)
2021-12-15 17:03 ` [PULL 092/102] ppc/pnv: Drop the "num-phbs" property Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices Cédric Le Goater
` (8 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++
hw/ppc/pnv.c | 12 ------------
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c
index a0526aa1eca3..c7426cd27a20 100644
--- a/hw/pci-host/pnv_phb3_pbcq.c
+++ b/hw/pci-host/pnv_phb3_pbcq.c
@@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev),
&pnv_pbcq_spci_xscom_ops, pbcq, name,
PNV_XSCOM_PBCQ_SPCI_SIZE);
+
+ /* Populate the XSCOM address space. */
+ pnv_xscom_add_subregion(phb->chip,
+ PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
+ &pbcq->xscom_nest_regs);
+ pnv_xscom_add_subregion(phb->chip,
+ PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
+ &pbcq->xscom_pci_regs);
+ pnv_xscom_add_subregion(phb->chip,
+ PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
+ &pbcq->xscom_spci_regs);
}
static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt,
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bbebd21d7522..c97fe77e88e6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1226,7 +1226,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
/* PHB3 controllers */
for (i = 0; i < chip->num_phbs; i++) {
PnvPHB3 *phb = &chip8->phbs[i];
- PnvPBCQState *pbcq = &phb->pbcq;
object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
@@ -1236,17 +1235,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
return;
}
-
- /* Populate the XSCOM address space. */
- pnv_xscom_add_subregion(chip,
- PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
- &pbcq->xscom_nest_regs);
- pnv_xscom_add_subregion(chip,
- PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
- &pbcq->xscom_pci_regs);
- pnv_xscom_add_subregion(chip,
- PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
- &pbcq->xscom_spci_regs);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices
2021-12-15 17:02 ` Cédric Le Goater
` (79 preceding siblings ...)
2021-12-15 17:03 ` [PULL 093/102] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 095/102] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices Cédric Le Goater
` (7 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 72 +++++++++++++++++++++++++++++++++++++++-------------
1 file changed, 54 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c97fe77e88e6..e75fc999ee11 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -638,16 +638,25 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
}
+static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque)
+{
+ Monitor *mon = opaque;
+ PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
+
+ if (phb3) {
+ pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
+ ics_pic_print_info(&phb3->lsis, mon);
+ }
+ return 0;
+}
+
static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
- int i;
ics_pic_print_info(&chip8->psi.ics, mon);
- for (i = 0; i < chip->num_phbs; i++) {
- pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
- ics_pic_print_info(&chip8->phbs[i].lsis, mon);
- }
+ object_child_foreach(OBJECT(chip),
+ pnv_chip_power8_pic_print_info_child, mon);
}
static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
@@ -1789,10 +1798,32 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
return NULL;
}
+typedef struct ForeachPhb3Args {
+ int irq;
+ ICSState *ics;
+} ForeachPhb3Args;
+
+static int pnv_ics_get_child(Object *child, void *opaque)
+{
+ ForeachPhb3Args *args = opaque;
+ PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
+
+ if (phb3) {
+ if (ics_valid_irq(&phb3->lsis, args->irq)) {
+ args->ics = &phb3->lsis;
+ }
+ if (ics_valid_irq(ICS(&phb3->msis), args->irq)) {
+ args->ics = ICS(&phb3->msis);
+ }
+ }
+ return args->ics ? 1 : 0;
+}
+
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
- int i, j;
+ ForeachPhb3Args args = { irq, NULL };
+ int i;
for (i = 0; i < pnv->num_chips; i++) {
PnvChip *chip = pnv->chips[i];
@@ -1801,32 +1832,37 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
if (ics_valid_irq(&chip8->psi.ics, irq)) {
return &chip8->psi.ics;
}
- for (j = 0; j < chip->num_phbs; j++) {
- if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
- return &chip8->phbs[j].lsis;
- }
- if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
- return ICS(&chip8->phbs[j].msis);
- }
+
+ object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args);
+ if (args.ics) {
+ return args.ics;
}
}
return NULL;
}
+static int pnv_ics_resend_child(Object *child, void *opaque)
+{
+ PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
+
+ if (phb3) {
+ ics_resend(&phb3->lsis);
+ ics_resend(ICS(&phb3->msis));
+ }
+ return 0;
+}
+
static void pnv_ics_resend(XICSFabric *xi)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
- int i, j;
+ int i;
for (i = 0; i < pnv->num_chips; i++) {
PnvChip *chip = pnv->chips[i];
Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
ics_resend(&chip8->psi.ics);
- for (j = 0; j < chip->num_phbs; j++) {
- ics_resend(&chip8->phbs[j].lsis);
- ics_resend(ICS(&chip8->phbs[j].msis));
- }
+ object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 095/102] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
2021-12-15 17:02 ` Cédric Le Goater
` (80 preceding siblings ...)
2021-12-15 17:03 ` [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices Cédric Le Goater
` (6 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 chip. Use that instead of num_phbs which fits POWER8 chips.
This will ease adding support for user created devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 2 ++
hw/ppc/pnv.c | 19 ++++++++-----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index aa08d79d24de..c781525277db 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -53,6 +53,7 @@ struct PnvChip {
PnvCore **cores;
uint32_t num_phbs;
+ uint32_t num_pecs;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
@@ -136,6 +137,7 @@ struct PnvChipClass {
uint64_t chip_cfam_id;
uint64_t cores_mask;
uint32_t num_phbs;
+ uint32_t num_pecs;
DeviceRealize parent_realize;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e75fc999ee11..2fc2b0dff7a3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -667,7 +667,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
pnv_xive_pic_print_info(&chip9->xive, mon);
pnv_psi_pic_print_info(&chip9->psi, mon);
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
for (j = 0; j < pec->num_stacks; j++) {
pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
@@ -1344,15 +1344,13 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ /* Number of PECs is the chip default */
+ chip->num_pecs = pcc->num_pecs;
+
+ for (i = 0; i < chip->num_pecs; i++) {
object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
TYPE_PNV_PHB4_PEC);
}
-
- /*
- * Number of PHBs is the chip default
- */
- chip->num_phbs = pcc->num_phbs;
}
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
@@ -1388,7 +1386,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
int i, j;
int phb_id = 0;
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
uint32_t pec_nest_base;
@@ -1416,8 +1414,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
- for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
- j++, phb_id++) {
+ for (j = 0; j < pec->num_stacks; j++, phb_id++) {
PnvPhb4PecStack *stack = &pec->stacks[j];
Object *obj = OBJECT(&stack->phb);
@@ -1573,7 +1570,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->xscom_core_base = pnv_chip_power9_xscom_core_base;
k->xscom_pcba = pnv_chip_power9_xscom_pcba;
dc->desc = "PowerNV Chip POWER9";
- k->num_phbs = 6;
+ k->num_pecs = PNV9_CHIP_MAX_PEC;
device_class_set_parent_realize(dc, pnv_chip_power9_realize,
&k->parent_realize);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
2021-12-15 17:02 ` Cédric Le Goater
` (81 preceding siblings ...)
2021-12-15 17:03 ` [PULL 095/102] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model Cédric Le Goater
` (5 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 27556ae53425..b2864233641e 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -219,6 +219,8 @@ struct PnvPhb4PecClass {
int compat_size;
const char *stk_compat;
int stk_compat_size;
+ uint64_t version;
+ uint64_t device_id;
};
#endif /* PCI_HOST_PNV_PHB4_H */
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 741ddc90ed8d..9f722729ac50 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -499,6 +499,8 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->compat_size = sizeof(compat);
pecc->stk_compat = stk_compat;
pecc->stk_compat_size = sizeof(stk_compat);
+ pecc->version = PNV_PHB4_VERSION;
+ pecc->device_id = PNV_PHB4_DEVICE_ID;
}
static const TypeInfo pnv_pec_type_info = {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2fc2b0dff7a3..78436a30ac0e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1421,9 +1421,9 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
object_property_set_int(obj, "index", phb_id, &error_fatal);
object_property_set_int(obj, "chip-id", chip->chip_id,
&error_fatal);
- object_property_set_int(obj, "version", PNV_PHB4_VERSION,
+ object_property_set_int(obj, "version", pecc->version,
&error_fatal);
- object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID,
+ object_property_set_int(obj, "device-id", pecc->device_id,
&error_fatal);
object_property_set_link(obj, "stack", OBJECT(stack),
&error_abort);
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model
2021-12-15 17:02 ` Cédric Le Goater
` (82 preceding siblings ...)
2021-12-15 17:03 ` [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 098/102] ppc/pnv: Introduce a num_stack class attribute Cédric Le Goater
` (4 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 7 +++++++
hw/ppc/pnv.c | 2 ++
3 files changed, 11 insertions(+)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index b2864233641e..8a585c9a42f7 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -205,6 +205,8 @@ struct PnvPhb4PecState {
#define PHB4_PEC_MAX_STACKS 3
uint32_t num_stacks;
PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS];
+
+ PnvChip *chip;
};
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 9f722729ac50..4b32b5ae6ed4 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -382,6 +382,11 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
assert(pec->system_memory);
+ if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
+ error_setg(errp, "invalid PEC index: %d", pec->index);
+ return;
+ }
+
/* Create stacks */
for (i = 0; i < pec->num_stacks; i++) {
PnvPhb4PecStack *stack = &pec->stacks[i];
@@ -462,6 +467,8 @@ static Property pnv_pec_properties[] = {
DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0),
DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
+ DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
+ PnvChip *),
DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 78436a30ac0e..ceee63c4d01e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1402,6 +1402,8 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
&error_fatal);
object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
&error_fatal);
+ object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
+ &error_fatal);
object_property_set_link(OBJECT(pec), "system-memory",
OBJECT(get_system_memory()), &error_abort);
if (!qdev_realize(DEVICE(pec), NULL, errp)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 098/102] ppc/pnv: Introduce a num_stack class attribute
2021-12-15 17:02 ` Cédric Le Goater
` (83 preceding siblings ...)
2021-12-15 17:03 ` [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model Cédric Le Goater
` (3 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4.h | 1 +
hw/pci-host/pnv_phb4_pec.c | 12 +++++++++++-
hw/ppc/pnv.c | 7 -------
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 8a585c9a42f7..60de3031a622 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -223,6 +223,7 @@ struct PnvPhb4PecClass {
int stk_compat_size;
uint64_t version;
uint64_t device_id;
+ const uint32_t *num_stacks;
};
#endif /* PCI_HOST_PNV_PHB4_H */
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 4b32b5ae6ed4..293909b5cb90 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -377,6 +377,7 @@ static void pnv_pec_instance_init(Object *obj)
static void pnv_pec_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
char name[64];
int i;
@@ -387,6 +388,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
return;
}
+ pec->num_stacks = pecc->num_stacks[pec->index];
+
/* Create stacks */
for (i = 0; i < pec->num_stacks; i++) {
PnvPhb4PecStack *stack = &pec->stacks[i];
@@ -465,7 +468,6 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
static Property pnv_pec_properties[] = {
DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
- DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0),
DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
PnvChip *),
@@ -484,6 +486,13 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
}
+/*
+ * PEC0 -> 1 stack
+ * PEC1 -> 2 stacks
+ * PEC2 -> 3 stacks
+ */
+static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 };
+
static void pnv_pec_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -508,6 +517,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->stk_compat_size = sizeof(stk_compat);
pecc->version = PNV_PHB4_VERSION;
pecc->device_id = PNV_PHB4_DEVICE_ID;
+ pecc->num_stacks = pnv_pec_num_stacks;
}
static const TypeInfo pnv_pec_type_info = {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ceee63c4d01e..3957a8c3b1ae 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1393,13 +1393,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
uint32_t pec_pci_base;
object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
- /*
- * PEC0 -> 1 stack
- * PEC1 -> 2 stacks
- * PEC2 -> 3 stacks
- */
- object_property_set_int(OBJECT(pec), "num-stacks", i + 1,
- &error_fatal);
object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
&error_fatal);
object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model
2021-12-15 17:02 ` Cédric Le Goater
` (84 preceding siblings ...)
2021-12-15 17:03 ` [PULL 098/102] ppc/pnv: Introduce a num_stack class attribute Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 100/102] ppc/pnv: Remove "system-memory" property from PHB4 PEC Cédric Le Goater
` (2 subsequent siblings)
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 which has a different layout of stacks: 3 per PECs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb4_pec.c | 16 ++++++++++++++++
hw/ppc/pnv.c | 4 +---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 293909b5cb90..a7dd4173d598 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -374,6 +374,19 @@ static void pnv_pec_instance_init(Object *obj)
}
}
+static int pnv_pec_phb_offset(PnvPhb4PecState *pec)
+{
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ int index = pec->index;
+ int offset = 0;
+
+ while (index--) {
+ offset += pecc->num_stacks[index];
+ }
+
+ return offset;
+}
+
static void pnv_pec_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
@@ -394,8 +407,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
for (i = 0; i < pec->num_stacks; i++) {
PnvPhb4PecStack *stack = &pec->stacks[i];
Object *stk_obj = OBJECT(stack);
+ int phb_id = pnv_pec_phb_offset(pec) + i;
object_property_set_int(stk_obj, "stack-no", i, &error_abort);
+ object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort);
object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort);
if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) {
return;
@@ -538,6 +553,7 @@ static void pnv_pec_stk_instance_init(Object *obj)
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj);
object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4);
+ object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index");
}
static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3957a8c3b1ae..712200264be2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1384,7 +1384,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
int i, j;
- int phb_id = 0;
for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
@@ -1409,11 +1408,10 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
- for (j = 0; j < pec->num_stacks; j++, phb_id++) {
+ for (j = 0; j < pec->num_stacks; j++) {
PnvPhb4PecStack *stack = &pec->stacks[j];
Object *obj = OBJECT(&stack->phb);
- object_property_set_int(obj, "index", phb_id, &error_fatal);
object_property_set_int(obj, "chip-id", chip->chip_id,
&error_fatal);
object_property_set_int(obj, "version", pecc->version,
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 100/102] ppc/pnv: Remove "system-memory" property from PHB4 PEC
2021-12-15 17:02 ` Cédric Le Goater
` (85 preceding siblings ...)
2021-12-15 17:03 ` [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 101/102] ppc/pnv: Move realize of PEC stacks under the PEC model Cédric Le Goater
2021-12-15 17:03 ` [PULL 102/102] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices Cédric Le Goater
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Peter Maydell, Daniel Henrique Barboza,
Richard Henderson, Cédric Le Goater
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb4_pec.c | 6 +-----
hw/ppc/pnv.c | 2 --
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index a7dd4173d598..dfed2af0f7df 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -124,7 +124,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
{
PnvPhb4PecState *pec = stack->pec;
- MemoryRegion *sysmem = pec->system_memory;
+ MemoryRegion *sysmem = get_system_memory();
uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN];
uint64_t bar, mask, size;
char name[64];
@@ -394,8 +394,6 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
char name[64];
int i;
- assert(pec->system_memory);
-
if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
error_setg(errp, "invalid PEC index: %d", pec->index);
return;
@@ -486,8 +484,6 @@ static Property pnv_pec_properties[] = {
DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
PnvChip *),
- DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory,
- TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 712200264be2..57a5180bccf2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1396,8 +1396,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
&error_fatal);
object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
&error_fatal);
- object_property_set_link(OBJECT(pec), "system-memory",
- OBJECT(get_system_memory()), &error_abort);
if (!qdev_realize(DEVICE(pec), NULL, errp)) {
return;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 101/102] ppc/pnv: Move realize of PEC stacks under the PEC model
2021-12-15 17:02 ` Cédric Le Goater
` (86 preceding siblings ...)
2021-12-15 17:03 ` [PULL 100/102] ppc/pnv: Remove "system-memory" property from PHB4 PEC Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
2021-12-15 17:03 ` [PULL 102/102] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices Cédric Le Goater
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb4_pec.c | 34 ++++++++++++++++++++++++++++++----
hw/ppc/pnv.c | 37 ++++---------------------------------
2 files changed, 34 insertions(+), 37 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index dfed2af0f7df..24a3adcae326 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -556,6 +556,10 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
{
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev);
PnvPhb4PecState *pec = stack->pec;
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ PnvChip *chip = pec->chip;
+ uint32_t pec_nest_base;
+ uint32_t pec_pci_base;
char name[64];
assert(pec);
@@ -579,10 +583,32 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb),
&pnv_phb4_xscom_ops, &stack->phb, name, 0x40);
- /*
- * Let the machine/chip realize the PHB object to customize more
- * easily some fields
- */
+ object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id,
+ &error_fatal);
+ object_property_set_int(OBJECT(&stack->phb), "version", pecc->version,
+ &error_fatal);
+ object_property_set_int(OBJECT(&stack->phb), "device-id", pecc->device_id,
+ &error_fatal);
+ object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) {
+ return;
+ }
+
+ pec_nest_base = pecc->xscom_nest_base(pec);
+ pec_pci_base = pecc->xscom_pci_base(pec);
+
+ /* Populate the XSCOM address space. */
+ pnv_xscom_add_subregion(chip,
+ pec_nest_base + 0x40 * (stack->stack_no + 1),
+ &stack->nest_regs_mr);
+ pnv_xscom_add_subregion(chip,
+ pec_pci_base + 0x40 * (stack->stack_no + 1),
+ &stack->pci_regs_mr);
+ pnv_xscom_add_subregion(chip,
+ pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
+ 0x40 * stack->stack_no,
+ &stack->phb_regs_mr);
}
static Property pnv_pec_stk_properties[] = {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 57a5180bccf2..c0b47a7d8909 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1380,10 +1380,10 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
}
}
-static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
+static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
- int i, j;
+ int i;
for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
@@ -1405,35 +1405,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
-
- for (j = 0; j < pec->num_stacks; j++) {
- PnvPhb4PecStack *stack = &pec->stacks[j];
- Object *obj = OBJECT(&stack->phb);
-
- object_property_set_int(obj, "chip-id", chip->chip_id,
- &error_fatal);
- object_property_set_int(obj, "version", pecc->version,
- &error_fatal);
- object_property_set_int(obj, "device-id", pecc->device_id,
- &error_fatal);
- object_property_set_link(obj, "stack", OBJECT(stack),
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {
- return;
- }
-
- /* Populate the XSCOM address space. */
- pnv_xscom_add_subregion(chip,
- pec_nest_base + 0x40 * (stack->stack_no + 1),
- &stack->nest_regs_mr);
- pnv_xscom_add_subregion(chip,
- pec_pci_base + 0x40 * (stack->stack_no + 1),
- &stack->pci_regs_mr);
- pnv_xscom_add_subregion(chip,
- pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
- 0x40 * stack->stack_no,
- &stack->phb_regs_mr);
- }
}
}
@@ -1529,8 +1500,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
&chip9->homer.regs);
- /* PHBs */
- pnv_chip_power9_phb_realize(chip, &local_err);
+ /* PEC PHBs */
+ pnv_chip_power9_pec_realize(chip, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread* [PULL 102/102] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
2021-12-15 17:02 ` Cédric Le Goater
` (87 preceding siblings ...)
2021-12-15 17:03 ` [PULL 101/102] ppc/pnv: Move realize of PEC stacks under the PEC model Cédric Le Goater
@ 2021-12-15 17:03 ` Cédric Le Goater
88 siblings, 0 replies; 111+ messages in thread
From: Cédric Le Goater @ 2021-12-15 17:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c0b47a7d8909..29ee0d0f08b4 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -659,20 +659,26 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
pnv_chip_power8_pic_print_info_child, mon);
}
+static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
+{
+ Monitor *mon = opaque;
+ PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
+
+ if (phb4) {
+ pnv_phb4_pic_print_info(phb4, mon);
+ }
+ return 0;
+}
+
static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
- int i, j;
pnv_xive_pic_print_info(&chip9->xive, mon);
pnv_psi_pic_print_info(&chip9->psi, mon);
- for (i = 0; i < chip->num_pecs; i++) {
- PnvPhb4PecState *pec = &chip9->pecs[i];
- for (j = 0; j < pec->num_stacks; j++) {
- pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
- }
- }
+ object_child_foreach_recursive(OBJECT(chip),
+ pnv_chip_power9_pic_print_info_child, mon);
}
static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
--
2.31.1
^ permalink raw reply related [flat|nested] 111+ messages in thread