Re: [PATCH v1 03/15] tcg: Fix register allocation constraints

[Richard Henderson <richard.henderson@linaro.org>]

On 8/13/24 21:34, LIU Zhiwei wrote:
> From: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
> 
> When allocating registers for input and output, ensure they match
> the available registers to avoid allocating illeagal registers.
> 
> We should respect RISC-V vector extension's variable-length registers
> and LMUL-based register grouping. Coordinate with tcg_target_available_regs
> initialization tcg_target_init (behind this commit) to ensure proper
> handling of vector register constraints.
> 
> Note: While mov_vec doesn't have constraints, dup_vec and other IRs do.
> We need to strengthen constraints for all IRs except mov_vec, and this
> is sufficient.
> 
> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
> Fixes: 29f5e92502 (tcg: Introduce paired register allocation)
> Reviewed-by: Liu Zhiwei<zhiwei_liu@linux.alibaba.com>
> ---
>   tcg/tcg.c | 20 +++++++++++++-------
>   1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 34e3056380..d26b42534d 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -4722,8 +4722,10 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
>           return;
>       }
>   
> -    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
> -    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
> +    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs &
> +                                    tcg_target_available_regs[ots->type];
> +    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs &
> +                                    tcg_target_available_regs[its->type];
>   

Why would you ever have constraints that resolve to unavailable registers?

If you don't want to fix this in the backend, then the next best place is in 
process_op_defs(), so that we take care of this once at startup, and never have to think 
about it again.


r~