Re: [PATCH v2 1/5] i386/tcg: implement x2APIC registers MSR access

[Bui Quang Minh <minhquangbui99@gmail.com>]

On 3/27/23 23:56, David Woodhouse wrote:
> On Sun, 2023-03-26 at 12:20 +0700, Bui Quang Minh wrote:
>>
>> +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
>> +                           unsigned size)
>> +{
>> +    int index = (addr >> 4) & 0xff;
>> +
>> +    if (size < 4) {
>> +        return;
>> +    }
>> +
>> +    if (addr > 0xfff || !index) {
>> +        /* MSI and MMIO APIC are at the same memory location,
>> +         * but actually not on the global bus: MSI is on PCI bus
>> +         * APIC is connected directly to the CPU.
>> +         * Mapping them on the global bus happens to work because
>> +         * MSI registers are reserved in APIC MMIO and vice versa.
>> */
>> +        MSIMessage msi = { .address = addr, .data = val };
>> +        apic_send_msi(&msi);
>> +        return;
>> +    }
> 
> I know you're just moving this bit around, but note that it means we
> *can't* implement the 15-bit MSI trick as things stand, because those
> extra 7 bits end up in bits 4-11 of the address, and that means the
> 'addr > 0xfff' check isn't correct any more.
> 
> However, that's only relevant in X2APIC mode... and there's no MMIO
> access to registers in X2APIC mode. So the check could perhaps become
> something like...
> 
>      DeviceState *apic = cpu_get_current_apic();
>      if (!apic || is_x2apic_mode(apic) || addr > 0xfff || !index) {
>          /* MSI and MMIO APIC are at the same memory location,
>           * but actually not on the global bus: MSI is on PCI bus
>           * APIC is connected directly to the CPU.
>           * Mapping them on the global bus happens to work because
>           * MSI registers are reserved in xAPIC MMIO and vice versa.
>           * In X2APIC mode, there is no MMIO and bits 4-11 of the
>           * address *might* be used to encode the extended dest ID.
>           */
> 
>          MSIMessage msi = ...

In my opinion, I think the with the emulated interrupt remap hardware we 
don't need to do MSI trick. The behavior is the same with real hardware, 
in order to use x2APIC an interrupt remap hardware is required, the OS 
will configure the interrupt source (IOxAPIC, MSI-capable) to use the 
remappable format for interrupt request.