From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction
Date: Mon, 9 Aug 2021 15:51:21 +0800 [thread overview]
Message-ID: <2fa362c9-d7a3-8aa3-13dd-ab46a525c977@c-sky.com> (raw)
In-Reply-To: <78383182-7c74-72dc-7bf6-e45c54b97a7e@linaro.org>
On 2021/8/6 上午6:17, Richard Henderson wrote:
> On 8/4/21 4:53 PM, LIU Zhiwei wrote:
>> static bool trans_srli(DisasContext *ctx, arg_srli *a)
>> {
>> + if (ctx->uxl32) {
>> + return trans_srliw(ctx, a);
>> + }
>> return gen_shifti(ctx, a, tcg_gen_shr_tl);
>> }
>
> First, trans_srliw begins with REQUIRE_64BIT, which *should* fail when
> RV32 is in effect. This means there's a missing change to is_32bit().
As I have replied in another patch, ctx->uxl32 already indicats 64 bit
CPU. Anyway, I will think more about how to merge is_32bit() and uxl32
in next patch set.
>
> Second, the current decode for srli allows 7 bits of shift, while
> srilw only allows 5. As a consequence, gen_shifti contains a check
> for TARGET_LONG_BITS and trans_srliw does not contain a check at all.
> We need to diagnose an out-of-range shift for RV32 somewhere.
>
Yes, it's not proper directly use *w here. Fix it in next patch set.
Zhiwei
> I recommend extending the gen_shift* family of helpers.
>
> static bool gen_shifti_imm(DisasContext *ctx, arg_shift *a, int width,
> void (*func)(TCGv, TCGv, target_long))
> {
> TCGv dest, src1;
>
> if (a->shamt >= width) {
> return false;
> }
> dest = gpr_dst(ctx, a->rd);
> src1 = gpr_src(ctx, a->rs1);
> func(dest, src1, a->shamt);
> return true;
> }
>
> static bool gen_shifti(DisasContext *ctx, arg_shift *a, int width,
> void (*func)(TCGv, TCGv, TCGv))
> {...}
>
> static void gen_srliw(TCGv dest, TCGv src1, target_long shamt)
> {
> tcg_gen_extract_tl(dest, src1, shamt, 32 - shamt);
> tcg_gen_ext32s_tl(dest, dest);
> }
>
> static bool trans_srliw(DisasContext *ctx, arg_shift *a)
> {
> REQUIRE_64BIT(ctx);
> return gen_shifti_imm(ctx, a, 32, gen_srliw);
> }
>
> static bool trans_srli(DisasContext *ctx, arg_shift *a)
> {
> int xlen = is_32bit(ctx) ? 32 : 64;
> return gen_shifti_imm(ctx, a, xlen,
> xlen == TARGET_LONG_BITS
> ? tcg_gen_shri_tl : gen_srliw);
> }
>
> etc. Perhaps that is_32bit() check above could be consolidated into
> some macro/inline.
>
>
> r~
next prev parent reply other threads:[~2021-08-09 7:54 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei
2021-08-05 6:00 ` Alistair Francis
2021-08-05 19:01 ` Richard Henderson
2021-08-06 2:49 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei
2021-08-05 19:06 ` Richard Henderson
2021-08-09 1:45 ` LIU Zhiwei
2021-08-09 19:34 ` Richard Henderson
2021-08-11 14:57 ` LIU Zhiwei
2021-08-11 17:56 ` Richard Henderson
2021-08-11 22:40 ` LIU Zhiwei
2021-08-12 4:42 ` Richard Henderson
2021-08-12 5:03 ` LIU Zhiwei
2021-08-12 6:12 ` Richard Henderson
2021-08-12 7:20 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei
2021-08-05 19:08 ` Richard Henderson
2021-08-09 1:50 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei
2021-08-05 19:09 ` Richard Henderson
2021-08-09 7:28 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei
2021-08-05 22:17 ` Richard Henderson
2021-08-09 7:51 ` LIU Zhiwei [this message]
2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei
2021-08-05 22:18 ` Richard Henderson
2021-08-09 7:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei
2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis
2021-08-05 7:14 ` LIU Zhiwei
2021-08-05 7:20 ` Bin Meng
2021-08-05 8:10 ` LIU Zhiwei
2021-08-06 10:05 ` Alistair Francis
2021-08-09 1:25 ` LIU Zhiwei
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