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[213.106.181.179]) by smtp.gmail.com with ESMTPSA id o1-20020a056000010100b003144bfbd0b3sm9215601wrx.37.2023.07.23.02.54.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Jul 2023 02:54:47 -0700 (PDT) Message-ID: <2ffa4ff5-56e8-1f4b-a5e4-df3eed4004d8@linaro.org> Date: Sun, 23 Jul 2023 10:54:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 03/14] target/arm/ptw: Set s1ns bit in fault info more consistently Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20230714154648.327466-1-peter.maydell@linaro.org> <20230714154648.327466-4-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20230714154648.327466-4-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/14/23 16:46, Peter Maydell wrote: > The s1ns bit in ARMMMUFaultInfo is documented as "true if > we faulted on a non-secure IPA while in secure state". Both the > places which look at this bit only do so after having confirmed > that this is a stage 2 fault and we're dealing with Secure EL2, > which leaves the ptw.c code free to set the bit to any random > value in the other cases. > > Instead of taking advantage of that freedom, consistently > make the bit be set to false for the "not a stage 2 fault > for Secure EL2" cases. This removes some cases where we > were using an 'is_secure' boolean and leaving the reader > guessing about whether that was the right thing for Realm > and Root cases. > > Signed-off-by: Peter Maydell > --- > target/arm/ptw.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~