From: Richard Henderson <richard.henderson@linaro.org>
To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
qemu-devel@nongnu.org, laurent@vivier.eu
Subject: Re: [PATCH 2/2] target/m68k: add M68K_FEATURE_NO_DALIGN feature
Date: Sun, 7 Mar 2021 17:03:15 -0800 [thread overview]
Message-ID: <301be535-ae3f-4c09-3be5-8efc4c799ea1@linaro.org> (raw)
In-Reply-To: <20210307202607.27745-3-mark.cave-ayland@ilande.co.uk>
On 3/7/21 12:26 PM, Mark Cave-Ayland wrote:
> According to the M68040UM Appendix D the requirement for data accesses to be
> word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
> 68020 onwards will allow unaligned data accesses but at the cost of being less
> efficient.
>
> Add a new M68K_FEATURE_NO_DALIGN feature to specify that data accesses are not
> required to be word aligned, and don't perform the alignment on the stack
> pointer when taking an exception if this feature is not selected.
How about a positive, rather than negative name, like M68K_FEATURE_UNALIGNED_DATA?
This points out that we should be raising Address Error without this feature.
This requires a moderate amount of cleanup in translate, manipulating
MO_ALIGN{,_2} as part of the MemOp parameter to tcg_gen_qemu_{ld,st}_i32.
r~
next prev parent reply other threads:[~2021-03-08 1:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-07 20:26 [PATCH 0/2] target/m68k: MacOS related fixes Mark Cave-Ayland
2021-03-07 20:26 ` [PATCH 1/2] target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland
2021-03-07 20:58 ` Laurent Vivier
2021-03-07 20:26 ` [PATCH 2/2] target/m68k: add M68K_FEATURE_NO_DALIGN feature Mark Cave-Ayland
2021-03-07 20:58 ` Laurent Vivier
2021-03-08 1:03 ` Richard Henderson [this message]
2021-03-08 12:05 ` Mark Cave-Ayland
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