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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id q2-20020a9d6542000000b0067088ff2b45sm9381708otl.37.2023.01.12.11.14.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 11:14:39 -0800 (PST) Message-ID: <3044a2d0-9e77-c936-b6e3-dfd9ad7d2c06@roeck-us.net> Date: Thu, 12 Jan 2023 11:14:36 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Content-Language: en-US To: Klaus Jensen , Keith Busch Cc: Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org, qemu-block@nongnu.org, qemu-devel@nongnu.org References: From: Guenter Roeck Subject: Re: completion timeouts with pin-based interrupts in QEMU hw/nvme In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=groeck7@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.067, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/12/23 09:45, Klaus Jensen wrote: > On Jan 12 09:34, Keith Busch wrote: >> On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote: >>> >>> The pin-based interrupt logic in hw/nvme seems sound enough to me, so I >>> am wondering if there is something going on with the kernel driver (but >>> I certainly do not rule out that hw/nvme is at fault here, since >>> pin-based interrupts has also been a source of several issues in the >>> past). >> >> Does it work if you change the pci_irq_assert() back to pci_irq_pulse()? >> While probably not the "correct" thing to do, it has better results in >> my testing. >> > > A simple s/pci_irq_assert/pci_irq_pulse broke the device. However, > > diff --git i/hw/nvme/ctrl.c w/hw/nvme/ctrl.c > index 03760ddeae8c..0fc46dcb9ec4 100644 > --- i/hw/nvme/ctrl.c > +++ w/hw/nvme/ctrl.c > @@ -477,6 +477,7 @@ static void nvme_irq_check(NvmeCtrl *n) > return; > } > if (~intms & n->irq_status) { > + pci_irq_deassert(&n->parent_obj); > pci_irq_assert(&n->parent_obj); > } else { > pci_irq_deassert(&n->parent_obj); > > > seems to do the trick (pulse is the other way around, assert, then > deassert). > > Probably not the "correct" thing to do, but I'll take it since it seems > to fix it. On a simple boot loop I got the timeout about 1 out of 5. I'm > on ~20 runs now and have not encountered it. > > I'll see if I can set up a mips rootfs and test that. Guenter, what MIPS > machine/board(s) are you testing? See https://github.com/groeck/linux-build-test/blob/master/rootfs/mips/run-qemu-mips.sh and https://github.com/groeck/linux-build-test/blob/master/rootfs/mipsel/run-qemu-mipsel.sh I'll apply the change suggested above to my version of qemu (7.2.0) and give it a try. Guenter