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[86.222.93.116]) by smtp.gmail.com with ESMTPSA id t15sm159295wrx.17.2021.07.13.15.18.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jul 2021 15:18:19 -0700 (PDT) Subject: Re: [PATCH v2 4/5] hw/nvme: fix mmio read To: Klaus Jensen , qemu-devel@nongnu.org References: <20210713192428.950160-1-its@irrelevant.dk> <20210713192428.950160-5-its@irrelevant.dk> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <30506100-68db-1fa2-ab32-f9f446c7193a@redhat.com> Date: Wed, 14 Jul 2021 00:18:17 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210713192428.950160-5-its@irrelevant.dk> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.7, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.368, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , Thomas Huth , qemu-block@nongnu.org, Peter Maydell , Laurent Vivier , Klaus Jensen , Gollu Appalanaidu , Max Reitz , Stefan Hajnoczi , Keith Busch , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/13/21 9:24 PM, Klaus Jensen wrote: > From: Klaus Jensen > > The new PMR test unearthed a long-standing issue with MMIO reads on > big-endian hosts. > > Fix this by unconditionally storing all controller registers in little > endian. > > Cc: Gollu Appalanaidu > Reported-by: Peter Maydell > Signed-off-by: Klaus Jensen > --- > hw/nvme/ctrl.c | 304 ++++++++++++++++++++++++++++--------------------- > 1 file changed, 174 insertions(+), 130 deletions(-) > > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index 0449cc4dee9b..ddac9344a74e 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -439,10 +439,12 @@ static uint8_t nvme_sq_empty(NvmeSQueue *sq) > > static void nvme_irq_check(NvmeCtrl *n) > { > + uint32_t intms = le32_to_cpu(n->bar.intms); > + > if (msix_enabled(&(n->parent_obj))) { > return; > } > - if (~n->bar.intms & n->irq_status) { > + if (~intms & n->irq_status) { > pci_irq_assert(&n->parent_obj); > } else { > pci_irq_deassert(&n->parent_obj); > @@ -1289,7 +1291,7 @@ static void nvme_post_cqes(void *opaque) > if (ret) { > trace_pci_nvme_err_addr_write(addr); > trace_pci_nvme_err_cfs(); > - n->bar.csts = NVME_CSTS_FAILED; > + n->bar.csts = cpu_to_le64(NVME_CSTS_FAILED); The load/store API is safer than the cpu_to_X() one because it removes alignment problems. Here it becomes: stq_le_p(&n->bar.csts, NVME_CSTS_FAILED); > break; > } > QTAILQ_REMOVE(&cq->req_list, req, entry); > @@ -4022,7 +4024,7 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req) > trace_pci_nvme_err_invalid_create_sq_sqid(sqid); > return NVME_INVALID_QID | NVME_DNR; > } > - if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { > + if (unlikely(!qsize || qsize > NVME_CAP_MQES(le64_to_cpu(n->bar.cap)))) { And here: if (unlikely(!qsize || qsize > NVME_CAP_MQES(ldq_le_p(&n->bar.cap)))) { > trace_pci_nvme_err_invalid_create_sq_size(qsize); > return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; > } However for the BAR is likely aligned, so using the cpu_to() API shouldn't be a problem until we try to deprecate/remove it.