Re: [RFC v3 06/21] hw/arm/smmuv3: Thread SEC_SID through helper APIs

[Eric Auger <eric.auger@redhat.com>]

On 10/12/25 5:06 PM, Tao Tang wrote:
> Extend the register and queue helper routines to accept an explicit
> SEC_SID argument instead of hard-coding the non-secure bank.
>
> All existing callers are updated to pass SMMU_SEC_SID_NS, so the
> behavior remains identical. This prepares the code for handling
> additional security state banks in the future. So Non-secure state
> is the only state bank supported for now.
>
> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  hw/arm/smmuv3-internal.h | 21 +++++++++------------
>  hw/arm/smmuv3.c          | 15 ++++++++-------
>  2 files changed, 17 insertions(+), 19 deletions(-)
>
> diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
> index 858bc206a2..af0e0b32b3 100644
> --- a/hw/arm/smmuv3-internal.h
> +++ b/hw/arm/smmuv3-internal.h
> @@ -246,9 +246,8 @@ REG64(S_EVENTQ_IRQ_CFG0,    0x80b0)
>  REG32(S_EVENTQ_IRQ_CFG1,    0x80b8)
>  REG32(S_EVENTQ_IRQ_CFG2,    0x80bc)
>  
> -static inline int smmu_enabled(SMMUv3State *s)
> +static inline int smmu_enabled(SMMUv3State *s, SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      return FIELD_EX32(bank->cr[0], CR0, SMMUEN);
>  }
> @@ -276,16 +275,16 @@ static inline uint32_t smmuv3_idreg(int regoffset)
>      return smmuv3_ids[regoffset / 4];
>  }
>  
> -static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
> +static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s,
> +                                             SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      return FIELD_EX32(bank->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
>  }
>  
> -static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
> +static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s,
> +                                             SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      return FIELD_EX32(bank->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
>  }
> @@ -330,23 +329,21 @@ static inline void queue_cons_incr(SMMUQueue *q)
>      q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
>  }
>  
> -static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
> +static inline bool smmuv3_cmdq_enabled(SMMUv3State *s, SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      return FIELD_EX32(bank->cr[0], CR0, CMDQEN);
>  }
>  
> -static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
> +static inline bool smmuv3_eventq_enabled(SMMUv3State *s, SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      return FIELD_EX32(bank->cr[0], CR0, EVENTQEN);
>  }
>  
> -static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
> +static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type,
> +                                       SMMUSecSID sec_sid)
>  {
> -    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>      SMMUv3RegBank *bank = smmuv3_bank(s, sec_sid);
>      bank->cmdq.cons = FIELD_DP32(bank->cmdq.cons, CMDQ_CONS, ERR, err_type);
>  }
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 9c085ac678..6d05bb1310 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -57,7 +57,7 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
>  
>      switch (irq) {
>      case SMMU_IRQ_EVTQ:
> -        pulse = smmuv3_eventq_irq_enabled(s);
> +        pulse = smmuv3_eventq_irq_enabled(s, sec_sid);
>          break;
>      case SMMU_IRQ_PRIQ:
>          qemu_log_mask(LOG_UNIMP, "PRI not yet supported\n");
> @@ -77,7 +77,7 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq,
>          bank->gerror ^= new_gerrors;
>          trace_smmuv3_write_gerror(new_gerrors, bank->gerror);
>  
> -        pulse = smmuv3_gerror_irq_enabled(s);
> +        pulse = smmuv3_gerror_irq_enabled(s, sec_sid);
>          break;
>      }
>      }
> @@ -153,7 +153,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
>      SMMUQueue *q = &bank->eventq;
>      MemTxResult r;
>  
> -    if (!smmuv3_eventq_enabled(s)) {
> +    if (!smmuv3_eventq_enabled(s, sec_sid)) {
>          return MEMTX_ERROR;
>      }
>  
> @@ -176,8 +176,9 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
>  {
>      Evt evt = {};
>      MemTxResult r;
> +    SMMUSecSID sec_sid = SMMU_SEC_SID_NS;
>  
> -    if (!smmuv3_eventq_enabled(s)) {
> +    if (!smmuv3_eventq_enabled(s, sec_sid)) {
>          return;
>      }
>  
> @@ -1070,7 +1071,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
>  
>      qemu_mutex_lock(&s->mutex);
>  
> -    if (!smmu_enabled(s)) {
> +    if (!smmu_enabled(s, sec_sid)) {
>          if (FIELD_EX32(bank->gbpa, GBPA, ABORT)) {
>              status = SMMU_TRANS_ABORT;
>          } else {
> @@ -1300,7 +1301,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
>      SMMUQueue *q = &bank->cmdq;
>      SMMUCommandType type = 0;
>  
> -    if (!smmuv3_cmdq_enabled(s)) {
> +    if (!smmuv3_cmdq_enabled(s, sec_sid)) {
>          return 0;
>      }
>      /*
> @@ -1513,7 +1514,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
>  
>      if (cmd_error) {
>          trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error);
> -        smmu_write_cmdq_err(s, cmd_error);
> +        smmu_write_cmdq_err(s, cmd_error, sec_sid);
>          smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK);
>      }
>