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From: David Hildenbrand <david@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 5/8] cputlb: Fix size operand for tlb_fill on unaligned store
Date: Thu, 29 Aug 2019 08:57:02 +0200	[thread overview]
Message-ID: <30ef0e0e-9a7c-00d8-7ba1-f2c7713deff9@redhat.com> (raw)
In-Reply-To: <20190828231651.17176-6-richard.henderson@linaro.org>

On 29.08.19 01:16, Richard Henderson wrote:
> We are currently passing the size of the full write to
> the tlb_fill for the second page.  Instead pass the real
> size of the write to that page.
> 
> This argument is unused within all tlb_fill, except to be
> logged via tracing, so in practice this makes no difference.
> 
> But in a moment we'll need the value of size2 for watchpoints,
> and if we've computed the value we might as well use it.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  accel/tcg/cputlb.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index c9576bebcf..7fb67d2f05 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -1504,6 +1504,8 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
>          uintptr_t index2;
>          CPUTLBEntry *entry2;
>          target_ulong page2, tlb_addr2;
> +        size_t size2;
> +
>      do_unaligned_access:
>          /*
>           * Ensure the second page is in the TLB.  Note that the first page
> @@ -1511,13 +1513,14 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
>           * cannot evict the first.
>           */
>          page2 = (addr + size) & TARGET_PAGE_MASK;
> +        size2 = (addr + size) & ~TARGET_PAGE_MASK;
>          index2 = tlb_index(env, mmu_idx, page2);
>          entry2 = tlb_entry(env, mmu_idx, page2);
>          tlb_addr2 = tlb_addr_write(entry2);
>          if (!tlb_hit_page(tlb_addr2, page2)
>              && !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
>                                 page2 & TARGET_PAGE_MASK)) {
> -            tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE,
> +            tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
>                       mmu_idx, retaddr);
>          }
>  
> 

Reviewed-by: David Hildenbrand <david@redhat.com>

-- 

Thanks,

David / dhildenb


  reply	other threads:[~2019-08-29  6:58 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28 23:16 [Qemu-devel] [PATCH v2 0/8] exec: Cleanup watchpoints Richard Henderson
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 1/8] exec: Move user-only watchpoint stubs inline Richard Henderson
2019-08-29 16:58   ` Philippe Mathieu-Daudé
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 2/8] exec: Factor out core logic of check_watchpoint() Richard Henderson
2019-08-29 17:26   ` Philippe Mathieu-Daudé
2019-08-30  1:21     ` Richard Henderson
2019-08-30 17:52       ` Philippe Mathieu-Daudé
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 3/8] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK Richard Henderson
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 4/8] exec: Factor out cpu_watchpoint_address_matches Richard Henderson
2019-08-29 17:20   ` Philippe Mathieu-Daudé
2019-08-30  1:32     ` Richard Henderson
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 5/8] cputlb: Fix size operand for tlb_fill on unaligned store Richard Henderson
2019-08-29  6:57   ` David Hildenbrand [this message]
2019-08-29 16:59   ` Philippe Mathieu-Daudé
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 6/8] cputlb: Remove double-alignment in store_helper Richard Henderson
2019-08-29  6:57   ` David Hildenbrand
2019-08-29 17:00   ` Philippe Mathieu-Daudé
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 7/8] cputlb: Handle watchpoints via TLB_WATCHPOINT Richard Henderson
2019-08-29  6:57   ` David Hildenbrand
2019-08-29 17:15   ` Philippe Mathieu-Daudé
2019-08-28 23:16 ` [Qemu-devel] [PATCH v2 8/8] tcg: Check for watchpoints in probe_write() Richard Henderson

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