* [PATCH 1/5] target/ppc: Introduce powerpc_excp_books
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
@ 2022-01-24 18:46 ` Fabiano Rosas
2022-01-25 12:06 ` Cédric Le Goater
2022-01-24 18:46 ` [PATCH 2/5] target/ppc: Simplify powerpc_excp_books Fabiano Rosas
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-24 18:46 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for BookS CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 478 +++++++++++++++++++++++++++++++++++++++
1 file changed, 478 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a0c932cd16..08aca37f0a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_G2:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_G2:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7x5:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_IO: /* IO error exception */
+ case POWERPC_EXCP_RUNM: /* Run mode exception */
+ case POWERPC_EXCP_EMUL: /* Emulation trap exception */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
/*
* Note that this function should be greatly optimized when called
* with a constant excp, from ppc_hw_interrupt
@@ -1034,6 +1505,13 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_40x:
powerpc_excp_40x(cpu, excp);
break;
+ case POWERPC_EXCP_970:
+ case POWERPC_EXCP_POWER7:
+ case POWERPC_EXCP_POWER8:
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ powerpc_excp_books(cpu, excp);
+ break;
default:
powerpc_excp_legacy(cpu, excp);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/5] target/ppc: Introduce powerpc_excp_books
2022-01-24 18:46 ` [PATCH 1/5] target/ppc: Introduce powerpc_excp_books Fabiano Rosas
@ 2022-01-25 12:06 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:06 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> Introduce a new powerpc_excp function specific for BookS CPUs. This
> commit copies powerpc_excp_legacy verbatim so the next one has a clean
> diff.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 478 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 478 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index a0c932cd16..08aca37f0a 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
>
> +static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> +{
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> + int excp_model = env->excp_model;
> + target_ulong msr, new_msr, vector;
> + int srr0, srr1, lev = -1;
> +
> + if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> + }
> +
> + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> + " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> + excp, env->error_code);
> +
> + /* new srr1 value excluding must-be-zero bits */
> + if (excp_model == POWERPC_EXCP_BOOKE) {
> + msr = env->msr;
> + } else {
> + msr = env->msr & ~0x783f0000ULL;
> + }
> +
> + /*
> + * new interrupt handler msr preserves existing HV and ME unless
> + * explicitly overriden
> + */
> + new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> +
> + /* target registers */
> + srr0 = SPR_SRR0;
> + srr1 = SPR_SRR1;
> +
> + /*
> + * check for special resume at 0x100 from doze/nap/sleep/winkle on
> + * P7/P8/P9
> + */
> + if (env->resume_as_sreset) {
> + excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> + }
> +
> + /*
> + * Hypervisor emulation assistance interrupt only exists on server
> + * arch 2.05 server or later. We also don't want to generate it if
> + * we don't have HVB in msr_mask (PAPR mode).
> + */
> + if (excp == POWERPC_EXCP_HV_EMU
> +#if defined(TARGET_PPC64)
> + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> +#endif /* defined(TARGET_PPC64) */
> +
> + ) {
> + excp = POWERPC_EXCP_PROGRAM;
> + }
> +
> +#ifdef TARGET_PPC64
> + /*
> + * SPEU and VPU share the same IVOR but they exist in different
> + * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> + */
> + if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> + excp = POWERPC_EXCP_SPEU;
> + }
> +#endif
> +
> + vector = env->excp_vectors[excp];
> + if (vector == (target_ulong)-1ULL) {
> + cpu_abort(cs, "Raised an exception without defined vector %d\n",
> + excp);
> + }
> +
> + vector |= env->excp_prefix;
> +
> + switch (excp) {
> + case POWERPC_EXCP_CRITICAL: /* Critical input */
> + switch (excp_model) {
> + case POWERPC_EXCP_40x:
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> + break;
> + case POWERPC_EXCP_BOOKE:
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + case POWERPC_EXCP_G2:
> + break;
> + default:
> + goto excp_invalid;
> + }
> + break;
> + case POWERPC_EXCP_MCHECK: /* Machine check exception */
> + if (msr_me == 0) {
> + /*
> + * Machine check exception is not enabled. Enter
> + * checkstop state.
> + */
> + fprintf(stderr, "Machine check while not allowed. "
> + "Entering checkstop state\n");
> + if (qemu_log_separate()) {
> + qemu_log("Machine check while not allowed. "
> + "Entering checkstop state\n");
> + }
> + cs->halted = 1;
> + cpu_interrupt_exittb(cs);
> + }
> + if (env->msr_mask & MSR_HVB) {
> + /*
> + * ISA specifies HV, but can be delivered to guest with HV
> + * clear (e.g., see FWNMI in PAPR).
> + */
> + new_msr |= (target_ulong)MSR_HVB;
> + }
> +
> + /* machine check exceptions don't have ME set */
> + new_msr &= ~((target_ulong)1 << MSR_ME);
> +
> + /* XXX: should also have something loaded in DAR / DSISR */
> + switch (excp_model) {
> + case POWERPC_EXCP_40x:
> + srr0 = SPR_40x_SRR2;
> + srr1 = SPR_40x_SRR3;
> + break;
> + case POWERPC_EXCP_BOOKE:
> + /* FIXME: choose one or the other based on CPU type */
> + srr0 = SPR_BOOKE_MCSRR0;
> + srr1 = SPR_BOOKE_MCSRR1;
> +
> + env->spr[SPR_BOOKE_CSRR0] = env->nip;
> + env->spr[SPR_BOOKE_CSRR1] = msr;
> + break;
> + default:
> + break;
> + }
> + break;
> + case POWERPC_EXCP_DSI: /* Data storage exception */
> + trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> + break;
> + case POWERPC_EXCP_ISI: /* Instruction storage exception */
> + trace_ppc_excp_isi(msr, env->nip);
> + msr |= env->error_code;
> + break;
> + case POWERPC_EXCP_EXTERNAL: /* External input */
> + {
> + bool lpes0;
> +
> + cs = CPU(cpu);
> +
> + /*
> + * Exception targeting modifiers
> + *
> + * LPES0 is supported on POWER7/8/9
> + * LPES1 is not supported (old iSeries mode)
> + *
> + * On anything else, we behave as if LPES0 is 1
> + * (externals don't alter MSR:HV)
> + */
> +#if defined(TARGET_PPC64)
> + if (excp_model == POWERPC_EXCP_POWER7 ||
> + excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9 ||
> + excp_model == POWERPC_EXCP_POWER10) {
> + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> + } else
> +#endif /* defined(TARGET_PPC64) */
> + {
> + lpes0 = true;
> + }
> +
> + if (!lpes0) {
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + }
> + if (env->mpic_proxy) {
> + /* IACK the IRQ on delivery */
> + env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> + }
> + break;
> + }
> + case POWERPC_EXCP_ALIGN: /* Alignment exception */
> + /* Get rS/rD and rA from faulting opcode */
> + /*
> + * Note: the opcode fields will not be set properly for a
> + * direct store load/store, but nobody cares as nobody
> + * actually uses direct store segments.
> + */
> + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> + break;
> + case POWERPC_EXCP_PROGRAM: /* Program exception */
> + switch (env->error_code & ~0xF) {
> + case POWERPC_EXCP_FP:
> + if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
> + trace_ppc_excp_fp_ignore();
> + cs->exception_index = POWERPC_EXCP_NONE;
> + env->error_code = 0;
> + return;
> + }
> +
> + /*
> + * FP exceptions always have NIP pointing to the faulting
> + * instruction, so always use store_next and claim we are
> + * precise in the MSR.
> + */
> + msr |= 0x00100000;
> + env->spr[SPR_BOOKE_ESR] = ESR_FP;
> + break;
> + case POWERPC_EXCP_INVAL:
> + trace_ppc_excp_inval(env->nip);
> + msr |= 0x00080000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> + break;
> + case POWERPC_EXCP_PRIV:
> + msr |= 0x00040000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> + break;
> + case POWERPC_EXCP_TRAP:
> + msr |= 0x00020000;
> + env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> + break;
> + default:
> + /* Should never occur */
> + cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> + env->error_code);
> + break;
> + }
> + break;
> + case POWERPC_EXCP_SYSCALL: /* System call exception */
> + lev = env->error_code;
> +
> + if ((lev == 1) && cpu->vhyp) {
> + dump_hcall(env);
> + } else {
> + dump_syscall(env);
> + }
> +
> + /*
> + * We need to correct the NIP which in this case is supposed
> + * to point to the next instruction
> + */
> + env->nip += 4;
> +
> + /* "PAPR mode" built-in hypercall emulation */
> + if ((lev == 1) && cpu->vhyp) {
> + PPCVirtualHypervisorClass *vhc =
> + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> + vhc->hypercall(cpu->vhyp, cpu);
> + return;
> + }
> + if (lev == 1) {
> + new_msr |= (target_ulong)MSR_HVB;
> + }
> + break;
> + case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> + lev = env->error_code;
> + dump_syscall(env);
> + env->nip += 4;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> +
> + vector += lev * 0x20;
> +
> + env->lr = env->nip;
> + env->ctr = msr;
> + break;
> + case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> + case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> + case POWERPC_EXCP_DECR: /* Decrementer exception */
> + break;
> + case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> + /* FIT on 4xx */
> + trace_ppc_excp_print("FIT");
> + break;
> + case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> + trace_ppc_excp_print("WDT");
> + switch (excp_model) {
> + case POWERPC_EXCP_BOOKE:
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + default:
> + break;
> + }
> + break;
> + case POWERPC_EXCP_DTLB: /* Data TLB error */
> + case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> + break;
> + case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> + if (env->flags & POWERPC_FLAG_DE) {
> + /* FIXME: choose one or the other based on CPU type */
> + srr0 = SPR_BOOKE_DSRR0;
> + srr1 = SPR_BOOKE_DSRR1;
> +
> + env->spr[SPR_BOOKE_CSRR0] = env->nip;
> + env->spr[SPR_BOOKE_CSRR1] = msr;
> +
> + /* DBSR already modified by caller */
> + } else {
> + cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> + }
> + break;
> + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> + env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> + break;
> + case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> + break;
> + case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> + srr0 = SPR_BOOKE_CSRR0;
> + srr1 = SPR_BOOKE_CSRR1;
> + break;
> + case POWERPC_EXCP_RESET: /* System reset exception */
> + /* A power-saving exception sets ME, otherwise it is unchanged */
> + if (msr_pow) {
> + /* indicate that we resumed from power save mode */
> + msr |= 0x10000;
> + new_msr |= ((target_ulong)1 << MSR_ME);
> + }
> + if (env->msr_mask & MSR_HVB) {
> + /*
> + * ISA specifies HV, but can be delivered to guest with HV
> + * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> + */
> + new_msr |= (target_ulong)MSR_HVB;
> + } else {
> + if (msr_pow) {
> + cpu_abort(cs, "Trying to deliver power-saving system reset "
> + "exception %d with no HV support\n", excp);
> + }
> + }
> + break;
> + case POWERPC_EXCP_DSEG: /* Data segment exception */
> + case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> + case POWERPC_EXCP_TRACE: /* Trace exception */
> + break;
> + case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> + msr |= env->error_code;
> + /* fall through */
> + case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> + case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> + case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> + case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> + case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> + case POWERPC_EXCP_HV_EMU:
> + case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + break;
> + case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> + case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> + case POWERPC_EXCP_FU: /* Facility unavailable exception */
> +#ifdef TARGET_PPC64
> + env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> +#endif
> + break;
> + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> +#ifdef TARGET_PPC64
> + env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> +#endif
> + break;
> + case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> + trace_ppc_excp_print("PIT");
> + break;
> + case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> + case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> + case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> + switch (excp_model) {
> + case POWERPC_EXCP_602:
> + case POWERPC_EXCP_603:
> + case POWERPC_EXCP_G2:
> + /* Swap temporary saved registers with GPRs */
> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> + new_msr |= (target_ulong)1 << MSR_TGPR;
> + hreg_swap_gpr_tgpr(env);
> + }
> + /* fall through */
> + case POWERPC_EXCP_7x5:
> + ppc_excp_debug_sw_tlb(env, excp);
> +
> + msr |= env->crf[0] << 28;
> + msr |= env->error_code; /* key, D/I, S/L bits */
> + /* Set way using a LRU mechanism */
> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> + break;
> + default:
> + cpu_abort(cs, "Invalid TLB miss exception\n");
> + break;
> + }
> + break;
> + case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> + case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> + case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> + case POWERPC_EXCP_IO: /* IO error exception */
> + case POWERPC_EXCP_RUNM: /* Run mode exception */
> + case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> + case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> + case POWERPC_EXCP_DABR: /* Data address breakpoint */
> + case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> + case POWERPC_EXCP_SMI: /* System management interrupt */
> + case POWERPC_EXCP_THERM: /* Thermal interrupt */
> + case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> + case POWERPC_EXCP_VPUA: /* Vector assist exception */
> + case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> + case POWERPC_EXCP_MAINT: /* Maintenance exception */
> + case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> + case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> + cpu_abort(cs, "%s exception not implemented\n",
> + powerpc_excp_name(excp));
> + break;
> + default:
> + excp_invalid:
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> + break;
> + }
> +
> + /* Sanity check */
> + if (!(env->msr_mask & MSR_HVB)) {
> + if (new_msr & MSR_HVB) {
> + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
> + "no HV support\n", excp);
> + }
> + if (srr0 == SPR_HSRR0) {
> + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
> + "no HV support\n", excp);
> + }
> + }
> +
> + /*
> + * Sort out endianness of interrupt, this differs depending on the
> + * CPU, the HV mode, etc...
> + */
> + if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> + new_msr |= (target_ulong)1 << MSR_LE;
> + }
> +
> +#if defined(TARGET_PPC64)
> + if (excp_model == POWERPC_EXCP_BOOKE) {
> + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> + new_msr |= (target_ulong)1 << MSR_CM;
> + } else {
> + vector = (uint32_t)vector;
> + }
> + } else {
> + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> + vector = (uint32_t)vector;
> + } else {
> + new_msr |= (target_ulong)1 << MSR_SF;
> + }
> + }
> +#endif
> +
> + if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> + /* Save PC */
> + env->spr[srr0] = env->nip;
> +
> + /* Save MSR */
> + env->spr[srr1] = msr;
> + }
> +
> + /* This can update new_msr and vector if AIL applies */
> + ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> +
> + powerpc_set_excp_state(cpu, vector, new_msr);
> +}
> +
> /*
> * Note that this function should be greatly optimized when called
> * with a constant excp, from ppc_hw_interrupt
> @@ -1034,6 +1505,13 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
> case POWERPC_EXCP_40x:
> powerpc_excp_40x(cpu, excp);
> break;
> + case POWERPC_EXCP_970:
> + case POWERPC_EXCP_POWER7:
> + case POWERPC_EXCP_POWER8:
> + case POWERPC_EXCP_POWER9:
> + case POWERPC_EXCP_POWER10:
> + powerpc_excp_books(cpu, excp);
> + break;
> default:
> powerpc_excp_legacy(cpu, excp);
> }
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/5] target/ppc: Simplify powerpc_excp_books
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
2022-01-24 18:46 ` [PATCH 1/5] target/ppc: Introduce powerpc_excp_books Fabiano Rosas
@ 2022-01-24 18:46 ` Fabiano Rosas
2022-01-25 12:09 ` Cédric Le Goater
2022-01-24 18:46 ` [PATCH 3/5] target/ppc: books: Machine Check exception cleanup Fabiano Rosas
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-24 18:46 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- Always uses HV_EMU if the CPU has MSR_HV;
- Exceptions always delivered in 64 bit.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSEG
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_FU
POWERPC_EXCP_HDECR
POWERPC_EXCP_HDSI
POWERPC_EXCP_HISI
POWERPC_EXCP_HVIRT
POWERPC_EXCP_HV_EMU
POWERPC_EXCP_HV_FU
POWERPC_EXCP_ISEG
POWERPC_EXCP_ISI
POWERPC_EXCP_MAINT
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SDOOR_HV
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_SYSCALL_VECTORED
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA
POWERPC_EXCP_VSXU
POWERPC_EXCP_HV_MAINT
POWERPC_EXCP_SDOOR
(I added the two above that were not being considered. They used to be
"Invalid exception". Now they become "Unimplemented exception" which
is more accurate.)
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 161 ++++-----------------------------------
1 file changed, 14 insertions(+), 147 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 08aca37f0a..0d27dfb2c5 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -551,6 +551,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+#ifdef TARGET_PPC64
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -568,11 +569,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
* new interrupt handler msr preserves existing HV and ME unless
@@ -593,29 +590,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
/*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * We don't want to generate a Hypervisor Emulation Assistance
+ * Interrupt if we don't have HVB in msr_mask (PAPR mode).
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -625,22 +606,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vector |= env->excp_prefix;
switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_G2:
- break;
- default:
- goto excp_invalid;
- }
- break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
/*
@@ -817,50 +782,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
env->ctr = msr;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -890,8 +813,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
/* fall through */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
case POWERPC_EXCP_HV_EMU:
case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
@@ -903,70 +824,25 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
break;
case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
- break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_IO: /* IO error exception */
- case POWERPC_EXCP_RUNM: /* Run mode exception */
- case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
- case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
+ case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
@@ -991,22 +867,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)1 << MSR_LE;
}
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
+ new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
/* Save PC */
@@ -1021,6 +882,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+#else
+static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
+{
+ g_assert_not_reached();
+}
+#endif
/*
* Note that this function should be greatly optimized when called
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 2/5] target/ppc: Simplify powerpc_excp_books
2022-01-24 18:46 ` [PATCH 2/5] target/ppc: Simplify powerpc_excp_books Fabiano Rosas
@ 2022-01-25 12:09 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:09 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> Differences from the generic powerpc_excp code:
>
> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
> - Always uses HV_EMU if the CPU has MSR_HV;
> - Exceptions always delivered in 64 bit.
>
> Exceptions used:
>
> POWERPC_EXCP_ALIGN
> POWERPC_EXCP_DECR
> POWERPC_EXCP_DSEG
> POWERPC_EXCP_DSI
> POWERPC_EXCP_EXTERNAL
> POWERPC_EXCP_FPU
> POWERPC_EXCP_FU
> POWERPC_EXCP_HDECR
> POWERPC_EXCP_HDSI
> POWERPC_EXCP_HISI
> POWERPC_EXCP_HVIRT
> POWERPC_EXCP_HV_EMU
> POWERPC_EXCP_HV_FU
> POWERPC_EXCP_ISEG
> POWERPC_EXCP_ISI
> POWERPC_EXCP_MAINT
> POWERPC_EXCP_MCHECK
> POWERPC_EXCP_PERFM
> POWERPC_EXCP_PROGRAM
> POWERPC_EXCP_RESET
> POWERPC_EXCP_SDOOR_HV
> POWERPC_EXCP_SYSCALL
> POWERPC_EXCP_SYSCALL_VECTORED
> POWERPC_EXCP_THERM
> POWERPC_EXCP_TRACE
> POWERPC_EXCP_VPU
> POWERPC_EXCP_VPUA
> POWERPC_EXCP_VSXU
>
> POWERPC_EXCP_HV_MAINT
> POWERPC_EXCP_SDOOR
>
> (I added the two above that were not being considered. They used to be
> "Invalid exception". Now they become "Unimplemented exception" which
> is more accurate.)
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
I would prefer 'powerpc_excp_book3s' but no need to resend for that.
I will change it.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 161 ++++-----------------------------------
> 1 file changed, 14 insertions(+), 147 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 08aca37f0a..0d27dfb2c5 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -551,6 +551,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
>
> +#ifdef TARGET_PPC64
> static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> {
> CPUState *cs = CPU(cpu);
> @@ -568,11 +569,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> excp, env->error_code);
>
> /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> + msr = env->msr & ~0x783f0000ULL;
>
> /*
> * new interrupt handler msr preserves existing HV and ME unless
> @@ -593,29 +590,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> }
>
> /*
> - * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> + * We don't want to generate a Hypervisor Emulation Assistance
> + * Interrupt if we don't have HVB in msr_mask (PAPR mode).
> */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> + if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) {
> excp = POWERPC_EXCP_PROGRAM;
> }
>
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> cpu_abort(cs, "Raised an exception without defined vector %d\n",
> @@ -625,22 +606,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> vector |= env->excp_prefix;
>
> switch (excp) {
> - case POWERPC_EXCP_CRITICAL: /* Critical input */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_G2:
> - break;
> - default:
> - goto excp_invalid;
> - }
> - break;
> case POWERPC_EXCP_MCHECK: /* Machine check exception */
> if (msr_me == 0) {
> /*
> @@ -817,50 +782,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> env->ctr = msr;
> break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> case POWERPC_EXCP_DECR: /* Decrementer exception */
> break;
> - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - /* FIT on 4xx */
> - trace_ppc_excp_print("FIT");
> - break;
> - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> - trace_ppc_excp_print("WDT");
> - switch (excp_model) {
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DTLB: /* Data TLB error */
> - case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> - break;
> - case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> - if (env->flags & POWERPC_FLAG_DE) {
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_DSRR0;
> - srr1 = SPR_BOOKE_DSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> -
> - /* DBSR already modified by caller */
> - } else {
> - cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> - }
> - break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> case POWERPC_EXCP_RESET: /* System reset exception */
> /* A power-saving exception sets ME, otherwise it is unchanged */
> if (msr_pow) {
> @@ -890,8 +813,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> /* fall through */
> case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> case POWERPC_EXCP_HV_EMU:
> case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> @@ -903,70 +824,25 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> case POWERPC_EXCP_FU: /* Facility unavailable exception */
> -#ifdef TARGET_PPC64
> env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> break;
> case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> -#ifdef TARGET_PPC64
> env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> srr0 = SPR_HSRR0;
> srr1 = SPR_HSRR1;
> new_msr |= (target_ulong)MSR_HVB;
> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> break;
> - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> - trace_ppc_excp_print("PIT");
> - break;
> - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> - case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> - case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - switch (excp_model) {
> - case POWERPC_EXCP_602:
> - case POWERPC_EXCP_603:
> - case POWERPC_EXCP_G2:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7x5:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> - }
> - break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_IO: /* IO error exception */
> - case POWERPC_EXCP_RUNM: /* Run mode exception */
> - case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint */
> - case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> - case POWERPC_EXCP_SMI: /* System management interrupt */
> case POWERPC_EXCP_THERM: /* Thermal interrupt */
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> + case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
> + case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
> cpu_abort(cs, "%s exception not implemented\n",
> powerpc_excp_name(excp));
> break;
> default:
> - excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
> }
> @@ -991,22 +867,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> new_msr |= (target_ulong)1 << MSR_LE;
> }
>
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> + new_msr |= (target_ulong)1 << MSR_SF;
>
> if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> /* Save PC */
> @@ -1021,6 +882,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>
> powerpc_set_excp_state(cpu, vector, new_msr);
> }
> +#else
> +static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> +{
> + g_assert_not_reached();
> +}
> +#endif
>
> /*
> * Note that this function should be greatly optimized when called
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/5] target/ppc: books: Machine Check exception cleanup
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
2022-01-24 18:46 ` [PATCH 1/5] target/ppc: Introduce powerpc_excp_books Fabiano Rosas
2022-01-24 18:46 ` [PATCH 2/5] target/ppc: Simplify powerpc_excp_books Fabiano Rosas
@ 2022-01-24 18:46 ` Fabiano Rosas
2022-01-25 12:09 ` Cédric Le Goater
2022-01-24 18:46 ` [PATCH 4/5] target/ppc: books: External interrupt cleanup Fabiano Rosas
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-24 18:46 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
powerpc_excp_books is BookS only, so remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0d27dfb2c5..e5f09e1984 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -632,23 +632,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/5] target/ppc: books: Machine Check exception cleanup
2022-01-24 18:46 ` [PATCH 3/5] target/ppc: books: Machine Check exception cleanup Fabiano Rosas
@ 2022-01-25 12:09 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:09 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> powerpc_excp_books is BookS only, so remove 40x and BookE code.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 17 -----------------
> 1 file changed, 17 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 0d27dfb2c5..e5f09e1984 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -632,23 +632,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> /* machine check exceptions don't have ME set */
> new_msr &= ~((target_ulong)1 << MSR_ME);
>
> - /* XXX: should also have something loaded in DAR / DSISR */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_MCSRR0;
> - srr1 = SPR_BOOKE_MCSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> - break;
> - default:
> - break;
> - }
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception */
> trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/5] target/ppc: books: External interrupt cleanup
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-01-24 18:46 ` [PATCH 3/5] target/ppc: books: Machine Check exception cleanup Fabiano Rosas
@ 2022-01-24 18:46 ` Fabiano Rosas
2022-01-25 12:11 ` Cédric Le Goater
2022-01-24 18:46 ` [PATCH 5/5] target/ppc: books: Program exception cleanup Fabiano Rosas
2022-01-25 12:28 ` [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Cédric Le Goater
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-24 18:46 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Since this is now BookS only, we can simplify the code a bit and check
has_hv_mode instead of enumerating the exception models. LPES0 does
not make sense if there is no MSR_HV.
Note that QEMU does not support HV mode on 970 and POWER5+ so we don't
set MSR_HV in msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 30 +++++++-----------------------
1 file changed, 7 insertions(+), 23 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e5f09e1984..67faec3775 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
bool lpes0;
- cs = CPU(cpu);
-
/*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
+ * LPES0 is only taken into consideration if we support HV
+ * mode for this CPU.
*/
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
+ if (!env->has_hv_mode) {
+ break;
}
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
+
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 4/5] target/ppc: books: External interrupt cleanup
2022-01-24 18:46 ` [PATCH 4/5] target/ppc: books: External interrupt cleanup Fabiano Rosas
@ 2022-01-25 12:11 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:11 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> Since this is now BookS only, we can simplify the code a bit and check
> has_hv_mode instead of enumerating the exception models. LPES0 does
> not make sense if there is no MSR_HV.
>
> Note that QEMU does not support HV mode on 970 and POWER5+ so we don't
> set MSR_HV in msr_mask.
HV mode is not supported on POWER7 also.
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Anyhow,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 30 +++++++-----------------------
> 1 file changed, 7 insertions(+), 23 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e5f09e1984..67faec3775 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -644,39 +644,23 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> {
> bool lpes0;
>
> - cs = CPU(cpu);
> -
> /*
> - * Exception targeting modifiers
> - *
> - * LPES0 is supported on POWER7/8/9
> - * LPES1 is not supported (old iSeries mode)
> - *
> - * On anything else, we behave as if LPES0 is 1
> - * (externals don't alter MSR:HV)
> + * LPES0 is only taken into consideration if we support HV
> + * mode for this CPU.
> */
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8 ||
> - excp_model == POWERPC_EXCP_POWER9 ||
> - excp_model == POWERPC_EXCP_POWER10) {
> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - } else
> -#endif /* defined(TARGET_PPC64) */
> - {
> - lpes0 = true;
> + if (!env->has_hv_mode) {
> + break;
> }
>
> + lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> +
> if (!lpes0) {
> new_msr |= (target_ulong)MSR_HVB;
> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> srr0 = SPR_HSRR0;
> srr1 = SPR_HSRR1;
> }
> - if (env->mpic_proxy) {
> - /* IACK the IRQ on delivery */
> - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> - }
> +
> break;
> }
> case POWERPC_EXCP_ALIGN: /* Alignment exception */
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/5] target/ppc: books: Program exception cleanup
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-01-24 18:46 ` [PATCH 4/5] target/ppc: books: External interrupt cleanup Fabiano Rosas
@ 2022-01-24 18:46 ` Fabiano Rosas
2022-01-25 12:11 ` Cédric Le Goater
2022-01-25 12:28 ` [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Cédric Le Goater
5 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-24 18:46 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Remove setting of BookE registers.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 67faec3775..d1cce76e75 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -688,20 +688,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
* precise in the MSR.
*/
msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
/* Should never occur */
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 5/5] target/ppc: books: Program exception cleanup
2022-01-24 18:46 ` [PATCH 5/5] target/ppc: books: Program exception cleanup Fabiano Rosas
@ 2022-01-25 12:11 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:11 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> Remove setting of BookE registers.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 67faec3775..d1cce76e75 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -688,20 +688,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> * precise in the MSR.
> */
> msr |= 0x00100000;
> - env->spr[SPR_BOOKE_ESR] = ESR_FP;
> break;
> case POWERPC_EXCP_INVAL:
> trace_ppc_excp_inval(env->nip);
> msr |= 0x00080000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> break;
> case POWERPC_EXCP_PRIV:
> msr |= 0x00040000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> break;
> case POWERPC_EXCP_TRAP:
> msr |= 0x00020000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> break;
> default:
> /* Should never occur */
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n)
2022-01-24 18:46 [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-01-24 18:46 ` [PATCH 5/5] target/ppc: books: Program exception cleanup Fabiano Rosas
@ 2022-01-25 12:28 ` Cédric Le Goater
2022-01-25 14:54 ` Fabiano Rosas
5 siblings, 1 reply; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 12:28 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/24/22 19:46, Fabiano Rosas wrote:
> This series splits the exception code for BookS CPUs: 970, POWER5+,
> POWER7, POWER8, POWER9, POWER10. After dealing with the 405, let's go
> back to something more familiar to give everyone a break.
>
> No upfront fixes this time. The pseries code gets used a lot, so there
> are no obvious issues and the older BookS CPUs get the benefits by
> default since they are similar.
Super ! I think this series can go in directly. I would only change
the name to book3s because it fits better the current naming in QEMU
and Linux.
Thanks,
C.
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n)
2022-01-25 12:28 ` [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n) Cédric Le Goater
@ 2022-01-25 14:54 ` Fabiano Rosas
2022-01-25 15:15 ` Cédric Le Goater
0 siblings, 1 reply; 14+ messages in thread
From: Fabiano Rosas @ 2022-01-25 14:54 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: danielhb413, qemu-ppc, david
Cédric Le Goater <clg@kaod.org> writes:
> On 1/24/22 19:46, Fabiano Rosas wrote:
>> This series splits the exception code for BookS CPUs: 970, POWER5+,
>> POWER7, POWER8, POWER9, POWER10. After dealing with the 405, let's go
>> back to something more familiar to give everyone a break.
>>
>> No upfront fixes this time. The pseries code gets used a lot, so there
>> are no obvious issues and the older BookS CPUs get the benefits by
>> default since they are similar.
>
> Super ! I think this series can go in directly. I would only change
> the name to book3s because it fits better the current naming in QEMU
> and Linux.
Not that it matters that much, but QEMU emulates Books I and II as well,
doesn't it?
Book I, Power ISA User Instruction Set Architecture,
covers the base instruction set and related facilities
available to the application programmer.
Book II, Power ISA Virtual Environment Architecture,
defines the storage model and other instructions and
facilities that enable the application programmer to cre-
ate multithreaded programs and programs that interact
with certain physical realities of the computing environ-
ment.
Book III, Power ISA Operating Environment Architec-
ture, defines the supervisor instructions and related
facilities.
Anyway, I'm OK with either name.
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] target/ppc: powerpc_excp improvements [BookS] (4/n)
2022-01-25 14:54 ` Fabiano Rosas
@ 2022-01-25 15:15 ` Cédric Le Goater
0 siblings, 0 replies; 14+ messages in thread
From: Cédric Le Goater @ 2022-01-25 15:15 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/25/22 15:54, Fabiano Rosas wrote:
> Cédric Le Goater <clg@kaod.org> writes:
>
>> On 1/24/22 19:46, Fabiano Rosas wrote:
>>> This series splits the exception code for BookS CPUs: 970, POWER5+,
>>> POWER7, POWER8, POWER9, POWER10. After dealing with the 405, let's go
>>> back to something more familiar to give everyone a break.
>>>
>>> No upfront fixes this time. The pseries code gets used a lot, so there
>>> are no obvious issues and the older BookS CPUs get the benefits by
>>> default since they are similar.
>>
>> Super ! I think this series can go in directly. I would only change
>> the name to book3s because it fits better the current naming in QEMU
>> and Linux.
>
> Not that it matters that much, but QEMU emulates Books I and II as well,
> doesn't it?
yes. it's just a naming convention that we use everywhere. See :
https://www.kernel.org/doc/html/latest/powerpc/cpu_families.html
book3s is even a larger family, it includes all the 32bit ..
I would vote for 'book3s_arch2x' to be in sync with the is_book3s_arch2x()
helper.
Thanks,
C.
> Book I, Power ISA User Instruction Set Architecture,
> covers the base instruction set and related facilities
> available to the application programmer.
>
> Book II, Power ISA Virtual Environment Architecture,
> defines the storage model and other instructions and
> facilities that enable the application programmer to cre-
> ate multithreaded programs and programs that interact
> with certain physical realities of the computing environ-
> ment.
>
> Book III, Power ISA Operating Environment Architec-
> ture, defines the supervisor instructions and related
> facilities.
>
> Anyway, I'm OK with either name.
>
>>
>> Thanks,
>>
>> C.
^ permalink raw reply [flat|nested] 14+ messages in thread