From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Zhao Liu" <zhao1.liu@intel.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Alireza Sanaee" <alireza.sanaee@huawei.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Yongwei Ma <yongwei.ma@intel.com>
Subject: Re: [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic
Date: Tue, 29 Oct 2024 17:10:52 -0300 [thread overview]
Message-ID: <31e8dc51-f70f-44eb-a768-61cfa50eed5b@linaro.org> (raw)
In-Reply-To: <20241022135151.2052198-3-zhao1.liu@intel.com>
On 22/10/24 10:51, Zhao Liu wrote:
> Cache topology needs to be defined based on CPU topology levels. Thus,
> define CPU topology enumeration in qapi/machine.json to make it generic
> for all architectures.
>
> To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
> CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
> socket.
>
> Also, enumerate additional topology levels for non-i386 arches, and add
> a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
> with compatibility requirement of arch-specific cache topology models.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> Tested-by: Yongwei Ma <yongwei.ma@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> Changes since Patch v3:
> * Dropped "invalid" level to avoid an unsettable option. (Daniel)
> ---
> hw/i386/x86-common.c | 4 +-
> include/hw/i386/topology.h | 23 ++----
> qapi/machine-common.json | 44 +++++++++++-
> target/i386/cpu.c | 144 ++++++++++++++++++-------------------
> target/i386/cpu.h | 4 +-
> 5 files changed, 123 insertions(+), 96 deletions(-)
>
> diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c
> index b86c38212eab..bc360a9ea44b 100644
> --- a/hw/i386/x86-common.c
> +++ b/hw/i386/x86-common.c
> @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
>
> if (ms->smp.modules > 1) {
> env->nr_modules = ms->smp.modules;
> - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo);
> + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
> }
>
> if (ms->smp.dies > 1) {
> env->nr_dies = ms->smp.dies;
> - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
> + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
> }
>
> /*
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index 48b43edc5a90..b2c8bf2de158 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -39,7 +39,7 @@
> * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
> */
>
> -
> +#include "qapi/qapi-types-machine-common.h"
> #include "qemu/bitops.h"
>
> /*
> @@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo {
> unsigned threads_per_core;
> } X86CPUTopoInfo;
>
> -#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
> -
> -/*
> - * CPUTopoLevel is the general i386 topology hierarchical representation,
> - * ordered by increasing hierarchical relationship.
> - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
> - * or AMD (CPUID[0x80000026]).
> - */
> -enum CPUTopoLevel {
> - CPU_TOPO_LEVEL_SMT,
> - CPU_TOPO_LEVEL_CORE,
> - CPU_TOPO_LEVEL_MODULE,
> - CPU_TOPO_LEVEL_DIE,
> - CPU_TOPO_LEVEL_PACKAGE,
> - CPU_TOPO_LEVEL_MAX,
> -};
> +#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX
> @@ -341,18 +341,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
> return 0;
> }
>
> -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
> +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
> {
> switch (topo_level) {
> - case CPU_TOPO_LEVEL_INVALID:
> + case CPU_TOPOLOGY_LEVEL_INVALID:
Since we use an enum, I'd rather directly use CPU_TOPOLOGY_LEVEL__MAX.
Or maybe in this case ...
> return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
> - case CPU_TOPO_LEVEL_SMT:
> + case CPU_TOPOLOGY_LEVEL_THREAD:
> return CPUID_1F_ECX_TOPO_LEVEL_SMT;
> - case CPU_TOPO_LEVEL_CORE:
> + case CPU_TOPOLOGY_LEVEL_CORE:
> return CPUID_1F_ECX_TOPO_LEVEL_CORE;
> - case CPU_TOPO_LEVEL_MODULE:
> + case CPU_TOPOLOGY_LEVEL_MODULE:
> return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
> - case CPU_TOPO_LEVEL_DIE:
> + case CPU_TOPOLOGY_LEVEL_DIE:
> return CPUID_1F_ECX_TOPO_LEVEL_DIE;
> default:
/* Other types are not supported in QEMU. */
g_assert_not_reached();
... return CPUID_1F_ECX_TOPO_LEVEL_INVALID as default.
Can be cleaned on top, so:
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2024-10-29 20:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
2024-10-22 14:43 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
2024-10-29 20:10 ` Philippe Mathieu-Daudé [this message]
2024-11-01 2:38 ` Zhao Liu
2024-11-01 7:47 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 4/9] hw/core: Check smp cache topology support " Zhao Liu
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
2024-10-22 14:44 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-10-22 13:51 ` [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-28 9:07 ` [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
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