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From: Aditya Gupta <adityag@linux.ibm.com>
To: Harsh Prateek Bora <harshpb@linux.ibm.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Sourabh Jain" <sourabhjain@linux.ibm.com>,
	"Mahesh J Salgaonkar" <mahesh@linux.ibm.com>,
	"Hari Bathini" <hbathini@linux.ibm.com>
Subject: Re: [PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE
Date: Fri, 14 Mar 2025 00:26:44 +0530	[thread overview]
Message-ID: <32011f77-ed4d-4c26-92d0-5ec139f1daa0@linux.ibm.com> (raw)
In-Reply-To: <72b6c824-7767-4dce-901f-806d291e1d98@linux.ibm.com>

On 11/03/25 10:53, Harsh Prateek Bora wrote:

>
>
> On 2/17/25 12:49, Aditya Gupta wrote:
>> Add offsets for the processor state captured during MPIPL dump.
>>
>> This is incomplete. And might be implemented in future if the effort to
>> implement MPIPL is resumed again.
>
> Please use RFC prefix in next iteration of patch series until the 
> patches are requested to be merged.

Sorry I missed it, and just sent it as a normal patch series.

Will take care from next time.


>
>>
>> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>> ---
>>   hw/ppc/pnv_sbe.c | 27 +++++++++++++++++++++++++++
>>   1 file changed, 27 insertions(+)
>>
>> diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
>> index ee905df4e0a6..3b50667226b5 100644
>> --- a/hw/ppc/pnv_sbe.c
>> +++ b/hw/ppc/pnv_sbe.c
>> @@ -197,6 +197,25 @@ struct mdrt_table {
>>       __be64  padding;    /* unused */
>>   } __packed;
>>   +/*
>> + * Processor Dump Area
>> + *
>> + * This contains the information needed for having processor
>> + * state captured during a platform dump.
>> + */
>> +struct proc_dump_area {
>> +    __be32  thread_size;    /* Size of each thread register entry */
>> +#define PROC_DUMP_AREA_FORMAT_P9    0x1    /* P9 format */
>> +    uint8_t version;
>> +    uint8_t reserved[11];
>> +    __be64  alloc_addr;    /* Destination memory to place register 
>> data */
>> +    __be32  reserved2;
>> +    __be32  alloc_size;    /* Allocated size */
>> +    __be64  dest_addr;     /* Destination address */
>> +    __be32  reserved3;
>> +    __be32  act_size;      /* Actual data size */
>> +} __packed;
>> +
>
> Above should go into pnv_sbe.h and introduce when actually get used.

Sure, will take care of introducing only when used.


>
>>   static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
>>   {
>>       val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW 
>> do? */
>> @@ -281,6 +300,11 @@ static void pnv_mpipl_preserve_mem(void)
>>       cpu_physical_memory_write(MDRT_TABLE_BASE, mdrt, MDRT_TABLE_SIZE);
>>   }
>>   +static void pnv_mpipl_save_proc_regs(void)
>> +{
>> +    /* TODO: modify PROC_DUMP_AREA_BASE */
>> +}
>> +
>>   static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr,
>>                                          uint64_t val, unsigned size)
>>   {
>> @@ -307,6 +331,9 @@ static void pnv_sbe_power9_xscom_ctrl_write(void 
>> *opaque, hwaddr addr,
>>               /* Preserve the memory locations registered for MPIPL */
>>               pnv_mpipl_preserve_mem();
>>   +            /* Save processor state */
>> +            pnv_mpipl_save_proc_regs();
>
> Introduce when actually get implemented, otherwise doesnt need a 
> separate patch for this stub.

Okay, I planned to implement it in this patch itself. Will implement in v2.


Thanks,

- Aditya G


>
>> +
>>               /*
>>                * TODO: Pass `mpipl` node in device tree to signify next
>>                * boot is an MPIPL boot


  reply	other threads:[~2025-03-13 18:57 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-17  7:19 [PATCH 0/7] Implement MPIPL for PowerNV Aditya Gupta
2025-02-17  7:19 ` [PATCH 1/7] hw/ppc: Log S0/S1 Interrupt triggers by OPAL Aditya Gupta
2025-03-11  4:38   ` Harsh Prateek Bora
2025-03-13 18:43     ` Aditya Gupta
2025-02-17  7:19 ` [PATCH 2/7] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-03-11  4:45   ` Harsh Prateek Bora
2025-03-13 18:45     ` Aditya Gupta
2025-02-17  7:19 ` [PATCH 3/7] hw/ppc: Handle stash command in PowerNV SBE Aditya Gupta
2025-03-11  4:50   ` Harsh Prateek Bora
2025-03-13 18:46     ` Aditya Gupta
2025-02-17  7:19 ` [PATCH 4/7] hw/ppc: Add MDST/MDDT/MDRT table structures and offsets Aditya Gupta
2025-03-11  5:11   ` Harsh Prateek Bora
2025-03-13 18:50     ` Aditya Gupta
2025-02-17  7:19 ` [PATCH 5/7] hw/ppc: Preserve Memory Regions as per MDST/MDDT tables Aditya Gupta
2025-03-11  5:18   ` Harsh Prateek Bora
2025-03-13 18:54     ` Aditya Gupta
2025-02-17  7:19 ` [PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE Aditya Gupta
2025-03-11  5:23   ` Harsh Prateek Bora
2025-03-13 18:56     ` Aditya Gupta [this message]
2025-02-17  7:19 ` [PATCH 7/7] hw/ppc: Implement MPIPL in PowerNV Aditya Gupta
2025-03-11  5:41   ` Harsh Prateek Bora
2025-03-13 19:00     ` Aditya Gupta
2025-02-27  3:37 ` [PATCH 0/7] Implement MPIPL for PowerNV Nicholas Piggin
2025-02-27  6:23   ` Aditya Gupta

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