[PATCH 0/2] target/loongarch: Fix some TLB flush issues

[PATCH 0/2] target/loongarch: Fix some TLB flush issues

[Bibo Mao]

There are two problems with TLB flush, one is that loongArch TLB entry
should be invalidated with different ASID, the other is global TLB entry
should be skippped when calculating replaced TLB entry.

With these two patches, it improves VM boot time also. VM boot time from
generic qcow file reduces to 300 seconds from previous 600 seconds.

Bibo Mao (2):
  target/loongarch: Add missing TLB flush with different asid
  target/loongarch: Skip global TLB when calculating replaced TLB

 target/loongarch/tcg/tlb_helper.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)


base-commit: 37ad0e48e9fd58b170abbf31c18a994346f62ed7
-- 
2.39.3

[PATCH 1/2] target/loongarch: Add missing TLB flush with different asid

[Bibo Mao]

If asid is changed in function helper_csrwr_asid(), qemu TLB is flushed,
however loongArch TLB is still valid. So loongArch TLB need be invalidated
in function invalidate_tlb() with different asid and bit effective need
be cleared.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 8cfce48a29..f8fada5b9a 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -117,13 +117,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
     uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
     uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
     uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
-    uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
 
-    if (!tlb_e) {
-        return;
-    }
-
-    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
     tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
     pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
     mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
@@ -145,11 +139,19 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
 {
     LoongArchTLB *tlb;
     uint16_t csr_asid, tlb_asid, tlb_g;
+    uint8_t tlb_e;
 
     csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
     tlb = &env->tlb[index];
+    tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+    if (!tlb_e) {
+        return;
+    }
+
+    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
     tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
     tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+    /* QEMU TLB is flushed when asid is changed */
     if (tlb_g == 0 && tlb_asid != csr_asid) {
         return;
     }
-- 
2.39.3

Re: [PATCH 1/2] target/loongarch: Add missing TLB flush with different asid

[gaosong]

在 2025/10/9 上午10:59, Bibo Mao 写道:
> If asid is changed in function helper_csrwr_asid(), qemu TLB is flushed,
> however loongArch TLB is still valid. So loongArch TLB need be invalidated
> in function invalidate_tlb() with different asid and bit effective need
> be cleared.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 14 ++++++++------
>   1 file changed, 8 insertions(+), 6 deletions(-)
Signed-off-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 8cfce48a29..f8fada5b9a 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -117,13 +117,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
>       uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
>       uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
>       uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> -    uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
>   
> -    if (!tlb_e) {
> -        return;
> -    }
> -
> -    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
>       tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
>       pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
>       mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
> @@ -145,11 +139,19 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
>   {
>       LoongArchTLB *tlb;
>       uint16_t csr_asid, tlb_asid, tlb_g;
> +    uint8_t tlb_e;
>   
>       csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
>       tlb = &env->tlb[index];
> +    tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
> +    if (!tlb_e) {
> +        return;
> +    }
> +
> +    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
>       tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
>       tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> +    /* QEMU TLB is flushed when asid is changed */
>       if (tlb_g == 0 && tlb_asid != csr_asid) {
>           return;
>       }

[PATCH 2/2] target/loongarch: Skip global TLB when calculating replaced TLB

[Bibo Mao]

When new TLB entry is added, TLB index is calculated from invalid
entry at first and then from different ASID, and randomly at last.

With different ASID, global TLB should be skipped since ASID is not
useful when global TLB is added.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index f8fada5b9a..f1d183cb64 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -371,7 +371,7 @@ void helper_tlbfill(CPULoongArchState *env)
     uint16_t pagesize, stlb_ps;
     uint16_t asid, tlb_asid;
     LoongArchTLB *tlb;
-    uint8_t tlb_e;
+    uint8_t tlb_e, tlb_g;
 
     if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
         entryhi = env->CSR_TLBREHI;
@@ -400,7 +400,8 @@ void helper_tlbfill(CPULoongArchState *env)
             }
 
             tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
-            if (asid != tlb_asid) {
+            tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+            if (tlb_g == 0 && asid != tlb_asid) {
                 set = i;
             }
         }
@@ -423,7 +424,8 @@ void helper_tlbfill(CPULoongArchState *env)
             }
 
             tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
-            if (asid != tlb_asid) {
+            tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
+            if (tlb_g == 0 && asid != tlb_asid) {
                 index = i;
             }
         }
-- 
2.39.3

Re: [PATCH 2/2] target/loongarch: Skip global TLB when calculating replaced TLB

[gaosong]

在 2025/10/9 上午10:59, Bibo Mao 写道:
> When new TLB entry is added, TLB index is calculated from invalid
> entry at first and then from different ASID, and randomly at last.
>
> With different ASID, global TLB should be skipped since ASID is not
> useful when global TLB is added.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
Signed-off-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index f8fada5b9a..f1d183cb64 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -371,7 +371,7 @@ void helper_tlbfill(CPULoongArchState *env)
>       uint16_t pagesize, stlb_ps;
>       uint16_t asid, tlb_asid;
>       LoongArchTLB *tlb;
> -    uint8_t tlb_e;
> +    uint8_t tlb_e, tlb_g;
>   
>       if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
>           entryhi = env->CSR_TLBREHI;
> @@ -400,7 +400,8 @@ void helper_tlbfill(CPULoongArchState *env)
>               }
>   
>               tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> -            if (asid != tlb_asid) {
> +            tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> +            if (tlb_g == 0 && asid != tlb_asid) {
>                   set = i;
>               }
>           }
> @@ -423,7 +424,8 @@ void helper_tlbfill(CPULoongArchState *env)
>               }
>   
>               tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
> -            if (asid != tlb_asid) {
> +            tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
> +            if (tlb_g == 0 && asid != tlb_asid) {
>                   index = i;
>               }
>           }

Re: [PATCH 0/2] target/loongarch: Fix some TLB flush issues

[gaosong]

在 2025/10/9 上午10:59, Bibo Mao 写道:
> There are two problems with TLB flush, one is that loongArch TLB entry
> should be invalidated with different ASID, the other is global TLB entry
> should be skippped when calculating replaced TLB entry.
>
> With these two patches, it improves VM boot time also. VM boot time from
> generic qcow file reduces to 300 seconds from previous 600 seconds.
>
> Bibo Mao (2):
>    target/loongarch: Add missing TLB flush with different asid
>    target/loongarch: Skip global TLB when calculating replaced TLB
>
>   target/loongarch/tcg/tlb_helper.c | 22 +++++++++++++---------
>   1 file changed, 13 insertions(+), 9 deletions(-)
>
>
> base-commit: 37ad0e48e9fd58b170abbf31c18a994346f62ed7
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao

Re: [PATCH 0/2] target/loongarch: Fix some TLB flush issues

[Philippe Mathieu-Daudé]

On 14/10/25 12:01, gaosong wrote:
> 在 2025/10/9 上午10:59, Bibo Mao 写道:
>> There are two problems with TLB flush, one is that loongArch TLB entry
>> should be invalidated with different ASID, the other is global TLB entry
>> should be skippped when calculating replaced TLB entry.
>>
>> With these two patches, it improves VM boot time also. VM boot time from
>> generic qcow file reduces to 300 seconds from previous 600 seconds.
>>
>> Bibo Mao (2):
>>    target/loongarch: Add missing TLB flush with different asid
>>    target/loongarch: Skip global TLB when calculating replaced TLB
>>
>>   target/loongarch/tcg/tlb_helper.c | 22 +++++++++++++---------
>>   1 file changed, 13 insertions(+), 9 deletions(-)
>>
>>
>> base-commit: 37ad0e48e9fd58b170abbf31c18a994346f62ed7
> Reviewed-by: Song Gao <gaosong@loongson.cn>

Merged as 2e9ff01a912 & f72848e31fb.